13cf3183fSVarun Wadekar /* 250402b17SVarun Wadekar * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 43cf3183fSVarun Wadekar * Redistribution and use in source and binary forms, with or without 53cf3183fSVarun Wadekar * modification, are permitted provided that the following conditions are met: 63cf3183fSVarun Wadekar * 73cf3183fSVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 83cf3183fSVarun Wadekar * list of conditions and the following disclaimer. 93cf3183fSVarun Wadekar * 103cf3183fSVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 113cf3183fSVarun Wadekar * this list of conditions and the following disclaimer in the documentation 123cf3183fSVarun Wadekar * and/or other materials provided with the distribution. 133cf3183fSVarun Wadekar * 143cf3183fSVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 153cf3183fSVarun Wadekar * to endorse or promote products derived from this software without specific 163cf3183fSVarun Wadekar * prior written permission. 173cf3183fSVarun Wadekar * 183cf3183fSVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 193cf3183fSVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 203cf3183fSVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 213cf3183fSVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 223cf3183fSVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 233cf3183fSVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 243cf3183fSVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 253cf3183fSVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 263cf3183fSVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 273cf3183fSVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 283cf3183fSVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 293cf3183fSVarun Wadekar */ 303cf3183fSVarun Wadekar 3150cd8646SVarun Wadekar #include <arch_helpers.h> 3250cd8646SVarun Wadekar #include <assert.h> 3348afb167SVarun Wadekar #include <bl31.h> 3450cd8646SVarun Wadekar #include <bl_common.h> 353cf3183fSVarun Wadekar #include <console.h> 3650cd8646SVarun Wadekar #include <context.h> 3750cd8646SVarun Wadekar #include <context_mgmt.h> 381eed3838SVarun Wadekar #include <cortex_a57.h> 3950cd8646SVarun Wadekar #include <debug.h> 4050cd8646SVarun Wadekar #include <denver.h> 4150cd8646SVarun Wadekar #include <interrupt_mgmt.h> 425cb89c56SVarun Wadekar #include <mce.h> 4350cd8646SVarun Wadekar #include <platform.h> 443cf3183fSVarun Wadekar #include <tegra_def.h> 452b04f927SVarun Wadekar #include <tegra_platform.h> 4650cd8646SVarun Wadekar #include <tegra_private.h> 473cf3183fSVarun Wadekar #include <xlat_tables.h> 483cf3183fSVarun Wadekar 491eed3838SVarun Wadekar DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1) 501eed3838SVarun Wadekar extern uint64_t tegra_enable_l2_ecc_parity_prot; 511eed3838SVarun Wadekar 52b67a7c7cSVarun Wadekar /******************************************************************************* 53*ae8ac2d2SVarun Wadekar * Tegra186 CPU numbers in cluster #0 54*ae8ac2d2SVarun Wadekar ******************************************************************************* 55*ae8ac2d2SVarun Wadekar */ 56*ae8ac2d2SVarun Wadekar #define TEGRA186_CLUSTER0_CORE2 2 57*ae8ac2d2SVarun Wadekar #define TEGRA186_CLUSTER0_CORE3 3 58*ae8ac2d2SVarun Wadekar 59*ae8ac2d2SVarun Wadekar /******************************************************************************* 60b67a7c7cSVarun Wadekar * The Tegra power domain tree has a single system level power domain i.e. a 61b67a7c7cSVarun Wadekar * single root node. The first entry in the power domain descriptor specifies 62b67a7c7cSVarun Wadekar * the number of power domains at the highest power level. 63b67a7c7cSVarun Wadekar ******************************************************************************* 64b67a7c7cSVarun Wadekar */ 65b67a7c7cSVarun Wadekar const unsigned char tegra_power_domain_tree_desc[] = { 66b67a7c7cSVarun Wadekar /* No of root nodes */ 67b67a7c7cSVarun Wadekar 1, 68b67a7c7cSVarun Wadekar /* No of clusters */ 69b67a7c7cSVarun Wadekar PLATFORM_CLUSTER_COUNT, 70b67a7c7cSVarun Wadekar /* No of CPU cores - cluster0 */ 71b67a7c7cSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER, 72b67a7c7cSVarun Wadekar /* No of CPU cores - cluster1 */ 73b67a7c7cSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER 74b67a7c7cSVarun Wadekar }; 75b67a7c7cSVarun Wadekar 763cf3183fSVarun Wadekar /* 773cf3183fSVarun Wadekar * Table of regions to map using the MMU. 783cf3183fSVarun Wadekar */ 793cf3183fSVarun Wadekar static const mmap_region_t tegra_mmap[] = { 803cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 813cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 82e64ce3abSVarun Wadekar MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 83e64ce3abSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 843cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 853cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 863cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 873cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8849cbbc4eSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ 8949cbbc4eSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 9049cbbc4eSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ 9149cbbc4eSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 9249cbbc4eSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ 933cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 941eed3838SVarun Wadekar MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ 951eed3838SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 963cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 973cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 9850402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 9950402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 10050402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 10150402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 10250402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 10350402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 10467bc721bSVarun Wadekar MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 10567bc721bSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 1063cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 1073cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 10850402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 10950402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 1103cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 1113cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 112691bc22dSVarun Wadekar MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000, /* 128KB - ARM/Denver */ 113691bc22dSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 11416c7cd01SVarun Wadekar #if ENABLE_SMMU_DEVICE 11550402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x1000000, /* 64KB */ 1163cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 11716c7cd01SVarun Wadekar #endif 1183cf3183fSVarun Wadekar {0} 1193cf3183fSVarun Wadekar }; 1203cf3183fSVarun Wadekar 1213cf3183fSVarun Wadekar /******************************************************************************* 1223cf3183fSVarun Wadekar * Set up the pagetables as per the platform memory map & initialize the MMU 1233cf3183fSVarun Wadekar ******************************************************************************/ 1243cf3183fSVarun Wadekar const mmap_region_t *plat_get_mmio_map(void) 1253cf3183fSVarun Wadekar { 1263cf3183fSVarun Wadekar /* MMIO space */ 1273cf3183fSVarun Wadekar return tegra_mmap; 1283cf3183fSVarun Wadekar } 1293cf3183fSVarun Wadekar 1303cf3183fSVarun Wadekar /******************************************************************************* 1313cf3183fSVarun Wadekar * Handler to get the System Counter Frequency 1323cf3183fSVarun Wadekar ******************************************************************************/ 1339c2a3d8aSVarun Wadekar unsigned int plat_get_syscnt_freq2(void) 1343cf3183fSVarun Wadekar { 1355d74d68eSVarun Wadekar return 31250000; 1363cf3183fSVarun Wadekar } 1373cf3183fSVarun Wadekar 1383cf3183fSVarun Wadekar /******************************************************************************* 1393cf3183fSVarun Wadekar * Maximum supported UART controllers 1403cf3183fSVarun Wadekar ******************************************************************************/ 1413cf3183fSVarun Wadekar #define TEGRA186_MAX_UART_PORTS 7 1423cf3183fSVarun Wadekar 1433cf3183fSVarun Wadekar /******************************************************************************* 1443cf3183fSVarun Wadekar * This variable holds the UART port base addresses 1453cf3183fSVarun Wadekar ******************************************************************************/ 1463cf3183fSVarun Wadekar static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 1473cf3183fSVarun Wadekar 0, /* undefined - treated as an error case */ 1483cf3183fSVarun Wadekar TEGRA_UARTA_BASE, 1493cf3183fSVarun Wadekar TEGRA_UARTB_BASE, 1503cf3183fSVarun Wadekar TEGRA_UARTC_BASE, 1513cf3183fSVarun Wadekar TEGRA_UARTD_BASE, 1523cf3183fSVarun Wadekar TEGRA_UARTE_BASE, 1533cf3183fSVarun Wadekar TEGRA_UARTF_BASE, 1543cf3183fSVarun Wadekar TEGRA_UARTG_BASE, 1553cf3183fSVarun Wadekar }; 1563cf3183fSVarun Wadekar 1573cf3183fSVarun Wadekar /******************************************************************************* 1583cf3183fSVarun Wadekar * Retrieve the UART controller base to be used as the console 1593cf3183fSVarun Wadekar ******************************************************************************/ 1603cf3183fSVarun Wadekar uint32_t plat_get_console_from_id(int id) 1613cf3183fSVarun Wadekar { 1623cf3183fSVarun Wadekar if (id > TEGRA186_MAX_UART_PORTS) 1633cf3183fSVarun Wadekar return 0; 1643cf3183fSVarun Wadekar 1653cf3183fSVarun Wadekar return tegra186_uart_addresses[id]; 1663cf3183fSVarun Wadekar } 16750cd8646SVarun Wadekar 1681eed3838SVarun Wadekar /* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */ 1691eed3838SVarun Wadekar #define TEGRA186_VER_A02P 0x1201 1701eed3838SVarun Wadekar 1711eed3838SVarun Wadekar /******************************************************************************* 1721eed3838SVarun Wadekar * Handler for early platform setup 1731eed3838SVarun Wadekar ******************************************************************************/ 1741eed3838SVarun Wadekar void plat_early_platform_setup(void) 1751eed3838SVarun Wadekar { 1761eed3838SVarun Wadekar int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 1772b04f927SVarun Wadekar uint32_t chip_subrev, val; 1781eed3838SVarun Wadekar 1791eed3838SVarun Wadekar /* sanity check MCE firmware compatibility */ 1801eed3838SVarun Wadekar mce_verify_firmware_version(); 1811eed3838SVarun Wadekar 1821eed3838SVarun Wadekar /* 1831eed3838SVarun Wadekar * Enable ECC and Parity Protection for Cortex-A57 CPUs 1841eed3838SVarun Wadekar * for Tegra A02p SKUs 1851eed3838SVarun Wadekar */ 1861eed3838SVarun Wadekar if (impl != DENVER_IMPL) { 1871eed3838SVarun Wadekar 1881eed3838SVarun Wadekar /* get the major, minor and sub-version values */ 1891eed3838SVarun Wadekar chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) & 1901eed3838SVarun Wadekar SUBREVISION_MASK; 1911eed3838SVarun Wadekar 1921eed3838SVarun Wadekar /* prepare chip version number */ 1932b04f927SVarun Wadekar val = (tegra_get_chipid_major() << 12) | 1942b04f927SVarun Wadekar (tegra_get_chipid_minor() << 8) | 1952b04f927SVarun Wadekar chip_subrev; 1961eed3838SVarun Wadekar 1971eed3838SVarun Wadekar /* enable L2 ECC for Tegra186 A02P and beyond */ 1981eed3838SVarun Wadekar if (val >= TEGRA186_VER_A02P) { 1991eed3838SVarun Wadekar 2001eed3838SVarun Wadekar val = read_l2ctlr_el1(); 2011eed3838SVarun Wadekar val |= L2_ECC_PARITY_PROTECTION_BIT; 2021eed3838SVarun Wadekar write_l2ctlr_el1(val); 2031eed3838SVarun Wadekar 2041eed3838SVarun Wadekar /* 2051eed3838SVarun Wadekar * Set the flag to enable ECC/Parity Protection 2061eed3838SVarun Wadekar * when we exit System Suspend or Cluster Powerdn 2071eed3838SVarun Wadekar */ 2081eed3838SVarun Wadekar tegra_enable_l2_ecc_parity_prot = 1; 2091eed3838SVarun Wadekar } 2101eed3838SVarun Wadekar } 2111eed3838SVarun Wadekar } 2121eed3838SVarun Wadekar 21350cd8646SVarun Wadekar /* Secure IRQs for Tegra186 */ 21450cd8646SVarun Wadekar static const irq_sec_cfg_t tegra186_sec_irqs[] = { 21550cd8646SVarun Wadekar { 21650cd8646SVarun Wadekar TEGRA186_TOP_WDT_IRQ, 21750cd8646SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 21850cd8646SVarun Wadekar INTR_TYPE_EL3, 21950cd8646SVarun Wadekar }, 22050cd8646SVarun Wadekar { 22150cd8646SVarun Wadekar TEGRA186_AON_WDT_IRQ, 22250cd8646SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 22350cd8646SVarun Wadekar INTR_TYPE_EL3, 22450cd8646SVarun Wadekar }, 22550cd8646SVarun Wadekar }; 22650cd8646SVarun Wadekar 22750cd8646SVarun Wadekar /******************************************************************************* 22850cd8646SVarun Wadekar * Initialize the GIC and SGIs 22950cd8646SVarun Wadekar ******************************************************************************/ 23050cd8646SVarun Wadekar void plat_gic_setup(void) 23150cd8646SVarun Wadekar { 23250cd8646SVarun Wadekar tegra_gic_setup(tegra186_sec_irqs, 23350cd8646SVarun Wadekar sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); 23450cd8646SVarun Wadekar 23550cd8646SVarun Wadekar /* 23650cd8646SVarun Wadekar * Initialize the FIQ handler only if the platform supports any 23750cd8646SVarun Wadekar * FIQ interrupt sources. 23850cd8646SVarun Wadekar */ 23950cd8646SVarun Wadekar if (sizeof(tegra186_sec_irqs) > 0) 24050cd8646SVarun Wadekar tegra_fiq_handler_setup(); 24150cd8646SVarun Wadekar } 24248afb167SVarun Wadekar 24348afb167SVarun Wadekar /******************************************************************************* 24448afb167SVarun Wadekar * Return pointer to the BL31 params from previous bootloader 24548afb167SVarun Wadekar ******************************************************************************/ 24648afb167SVarun Wadekar bl31_params_t *plat_get_bl31_params(void) 24748afb167SVarun Wadekar { 24848afb167SVarun Wadekar uint32_t val; 24948afb167SVarun Wadekar 25048afb167SVarun Wadekar val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); 25148afb167SVarun Wadekar 25248afb167SVarun Wadekar return (bl31_params_t *)(uintptr_t)val; 25348afb167SVarun Wadekar } 25448afb167SVarun Wadekar 25548afb167SVarun Wadekar /******************************************************************************* 25648afb167SVarun Wadekar * Return pointer to the BL31 platform params from previous bootloader 25748afb167SVarun Wadekar ******************************************************************************/ 25848afb167SVarun Wadekar plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 25948afb167SVarun Wadekar { 26048afb167SVarun Wadekar uint32_t val; 26148afb167SVarun Wadekar 26248afb167SVarun Wadekar val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); 26348afb167SVarun Wadekar 26448afb167SVarun Wadekar return (plat_params_from_bl2_t *)(uintptr_t)val; 26548afb167SVarun Wadekar } 266*ae8ac2d2SVarun Wadekar 267*ae8ac2d2SVarun Wadekar /******************************************************************************* 268*ae8ac2d2SVarun Wadekar * This function implements a part of the critical interface between the psci 269*ae8ac2d2SVarun Wadekar * generic layer and the platform that allows the former to query the platform 270*ae8ac2d2SVarun Wadekar * to convert an MPIDR to a unique linear index. An error code (-1) is returned 271*ae8ac2d2SVarun Wadekar * in case the MPIDR is invalid. 272*ae8ac2d2SVarun Wadekar ******************************************************************************/ 273*ae8ac2d2SVarun Wadekar int plat_core_pos_by_mpidr(u_register_t mpidr) 274*ae8ac2d2SVarun Wadekar { 275*ae8ac2d2SVarun Wadekar unsigned int cluster_id, cpu_id, pos; 276*ae8ac2d2SVarun Wadekar 277*ae8ac2d2SVarun Wadekar cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 278*ae8ac2d2SVarun Wadekar cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 279*ae8ac2d2SVarun Wadekar 280*ae8ac2d2SVarun Wadekar /* 281*ae8ac2d2SVarun Wadekar * Validate cluster_id by checking whether it represents 282*ae8ac2d2SVarun Wadekar * one of the two clusters present on the platform. 283*ae8ac2d2SVarun Wadekar */ 284*ae8ac2d2SVarun Wadekar if (cluster_id >= PLATFORM_CLUSTER_COUNT) 285*ae8ac2d2SVarun Wadekar return PSCI_E_NOT_PRESENT; 286*ae8ac2d2SVarun Wadekar 287*ae8ac2d2SVarun Wadekar /* 288*ae8ac2d2SVarun Wadekar * Validate cpu_id by checking whether it represents a CPU in 289*ae8ac2d2SVarun Wadekar * one of the two clusters present on the platform. 290*ae8ac2d2SVarun Wadekar */ 291*ae8ac2d2SVarun Wadekar if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) 292*ae8ac2d2SVarun Wadekar return PSCI_E_NOT_PRESENT; 293*ae8ac2d2SVarun Wadekar 294*ae8ac2d2SVarun Wadekar /* calculate the core position */ 295*ae8ac2d2SVarun Wadekar pos = cpu_id + (cluster_id << 2); 296*ae8ac2d2SVarun Wadekar 297*ae8ac2d2SVarun Wadekar /* check for non-existent CPUs */ 298*ae8ac2d2SVarun Wadekar if (pos == TEGRA186_CLUSTER0_CORE2 || pos == TEGRA186_CLUSTER0_CORE3) 299*ae8ac2d2SVarun Wadekar return PSCI_E_NOT_PRESENT; 300*ae8ac2d2SVarun Wadekar 301*ae8ac2d2SVarun Wadekar return pos; 302*ae8ac2d2SVarun Wadekar } 303