13cf3183fSVarun Wadekar /* 250402b17SVarun Wadekar * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 43cf3183fSVarun Wadekar * Redistribution and use in source and binary forms, with or without 53cf3183fSVarun Wadekar * modification, are permitted provided that the following conditions are met: 63cf3183fSVarun Wadekar * 73cf3183fSVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 83cf3183fSVarun Wadekar * list of conditions and the following disclaimer. 93cf3183fSVarun Wadekar * 103cf3183fSVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 113cf3183fSVarun Wadekar * this list of conditions and the following disclaimer in the documentation 123cf3183fSVarun Wadekar * and/or other materials provided with the distribution. 133cf3183fSVarun Wadekar * 143cf3183fSVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 153cf3183fSVarun Wadekar * to endorse or promote products derived from this software without specific 163cf3183fSVarun Wadekar * prior written permission. 173cf3183fSVarun Wadekar * 183cf3183fSVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 193cf3183fSVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 203cf3183fSVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 213cf3183fSVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 223cf3183fSVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 233cf3183fSVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 243cf3183fSVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 253cf3183fSVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 263cf3183fSVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 273cf3183fSVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 283cf3183fSVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 293cf3183fSVarun Wadekar */ 303cf3183fSVarun Wadekar 3150cd8646SVarun Wadekar #include <arch_helpers.h> 3250cd8646SVarun Wadekar #include <assert.h> 3348afb167SVarun Wadekar #include <bl31.h> 3450cd8646SVarun Wadekar #include <bl_common.h> 353cf3183fSVarun Wadekar #include <console.h> 3650cd8646SVarun Wadekar #include <context.h> 3750cd8646SVarun Wadekar #include <context_mgmt.h> 381eed3838SVarun Wadekar #include <cortex_a57.h> 3950cd8646SVarun Wadekar #include <debug.h> 4050cd8646SVarun Wadekar #include <denver.h> 4150cd8646SVarun Wadekar #include <interrupt_mgmt.h> 425cb89c56SVarun Wadekar #include <mce.h> 4350cd8646SVarun Wadekar #include <platform.h> 443cf3183fSVarun Wadekar #include <tegra_def.h> 4550cd8646SVarun Wadekar #include <tegra_private.h> 463cf3183fSVarun Wadekar #include <xlat_tables.h> 473cf3183fSVarun Wadekar 481eed3838SVarun Wadekar DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1) 491eed3838SVarun Wadekar extern uint64_t tegra_enable_l2_ecc_parity_prot; 501eed3838SVarun Wadekar 51b67a7c7cSVarun Wadekar /******************************************************************************* 52b67a7c7cSVarun Wadekar * The Tegra power domain tree has a single system level power domain i.e. a 53b67a7c7cSVarun Wadekar * single root node. The first entry in the power domain descriptor specifies 54b67a7c7cSVarun Wadekar * the number of power domains at the highest power level. 55b67a7c7cSVarun Wadekar ******************************************************************************* 56b67a7c7cSVarun Wadekar */ 57b67a7c7cSVarun Wadekar const unsigned char tegra_power_domain_tree_desc[] = { 58b67a7c7cSVarun Wadekar /* No of root nodes */ 59b67a7c7cSVarun Wadekar 1, 60b67a7c7cSVarun Wadekar /* No of clusters */ 61b67a7c7cSVarun Wadekar PLATFORM_CLUSTER_COUNT, 62b67a7c7cSVarun Wadekar /* No of CPU cores - cluster0 */ 63b67a7c7cSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER, 64b67a7c7cSVarun Wadekar /* No of CPU cores - cluster1 */ 65b67a7c7cSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER 66b67a7c7cSVarun Wadekar }; 67b67a7c7cSVarun Wadekar 683cf3183fSVarun Wadekar /* 693cf3183fSVarun Wadekar * Table of regions to map using the MMU. 703cf3183fSVarun Wadekar */ 713cf3183fSVarun Wadekar static const mmap_region_t tegra_mmap[] = { 723cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 733cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 74e64ce3abSVarun Wadekar MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 75e64ce3abSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 763cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 773cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 783cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 793cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 803cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB */ 813cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 821eed3838SVarun Wadekar MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ 831eed3838SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 843cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 853cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8650402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 8750402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8850402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 8950402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 9050402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 9150402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 9267bc721bSVarun Wadekar MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 9367bc721bSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 943cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 953cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 9650402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 9750402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 983cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 993cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 10050402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x1000000, /* 64KB */ 1013cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 1023cf3183fSVarun Wadekar {0} 1033cf3183fSVarun Wadekar }; 1043cf3183fSVarun Wadekar 1053cf3183fSVarun Wadekar /******************************************************************************* 1063cf3183fSVarun Wadekar * Set up the pagetables as per the platform memory map & initialize the MMU 1073cf3183fSVarun Wadekar ******************************************************************************/ 1083cf3183fSVarun Wadekar const mmap_region_t *plat_get_mmio_map(void) 1093cf3183fSVarun Wadekar { 1103cf3183fSVarun Wadekar /* MMIO space */ 1113cf3183fSVarun Wadekar return tegra_mmap; 1123cf3183fSVarun Wadekar } 1133cf3183fSVarun Wadekar 1143cf3183fSVarun Wadekar /******************************************************************************* 1153cf3183fSVarun Wadekar * Handler to get the System Counter Frequency 1163cf3183fSVarun Wadekar ******************************************************************************/ 117*9c2a3d8aSVarun Wadekar unsigned int plat_get_syscnt_freq2(void) 1183cf3183fSVarun Wadekar { 1195d74d68eSVarun Wadekar return 31250000; 1203cf3183fSVarun Wadekar } 1213cf3183fSVarun Wadekar 1223cf3183fSVarun Wadekar /******************************************************************************* 1233cf3183fSVarun Wadekar * Maximum supported UART controllers 1243cf3183fSVarun Wadekar ******************************************************************************/ 1253cf3183fSVarun Wadekar #define TEGRA186_MAX_UART_PORTS 7 1263cf3183fSVarun Wadekar 1273cf3183fSVarun Wadekar /******************************************************************************* 1283cf3183fSVarun Wadekar * This variable holds the UART port base addresses 1293cf3183fSVarun Wadekar ******************************************************************************/ 1303cf3183fSVarun Wadekar static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 1313cf3183fSVarun Wadekar 0, /* undefined - treated as an error case */ 1323cf3183fSVarun Wadekar TEGRA_UARTA_BASE, 1333cf3183fSVarun Wadekar TEGRA_UARTB_BASE, 1343cf3183fSVarun Wadekar TEGRA_UARTC_BASE, 1353cf3183fSVarun Wadekar TEGRA_UARTD_BASE, 1363cf3183fSVarun Wadekar TEGRA_UARTE_BASE, 1373cf3183fSVarun Wadekar TEGRA_UARTF_BASE, 1383cf3183fSVarun Wadekar TEGRA_UARTG_BASE, 1393cf3183fSVarun Wadekar }; 1403cf3183fSVarun Wadekar 1413cf3183fSVarun Wadekar /******************************************************************************* 1423cf3183fSVarun Wadekar * Retrieve the UART controller base to be used as the console 1433cf3183fSVarun Wadekar ******************************************************************************/ 1443cf3183fSVarun Wadekar uint32_t plat_get_console_from_id(int id) 1453cf3183fSVarun Wadekar { 1463cf3183fSVarun Wadekar if (id > TEGRA186_MAX_UART_PORTS) 1473cf3183fSVarun Wadekar return 0; 1483cf3183fSVarun Wadekar 1493cf3183fSVarun Wadekar return tegra186_uart_addresses[id]; 1503cf3183fSVarun Wadekar } 15150cd8646SVarun Wadekar 1521eed3838SVarun Wadekar /* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */ 1531eed3838SVarun Wadekar #define TEGRA186_VER_A02P 0x1201 1541eed3838SVarun Wadekar 1551eed3838SVarun Wadekar /******************************************************************************* 1561eed3838SVarun Wadekar * Handler for early platform setup 1571eed3838SVarun Wadekar ******************************************************************************/ 1581eed3838SVarun Wadekar void plat_early_platform_setup(void) 1591eed3838SVarun Wadekar { 1601eed3838SVarun Wadekar int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 1611eed3838SVarun Wadekar uint32_t chip_minor, chip_major, chip_subrev, val; 1621eed3838SVarun Wadekar 1631eed3838SVarun Wadekar /* sanity check MCE firmware compatibility */ 1641eed3838SVarun Wadekar mce_verify_firmware_version(); 1651eed3838SVarun Wadekar 1661eed3838SVarun Wadekar /* 1671eed3838SVarun Wadekar * Enable ECC and Parity Protection for Cortex-A57 CPUs 1681eed3838SVarun Wadekar * for Tegra A02p SKUs 1691eed3838SVarun Wadekar */ 1701eed3838SVarun Wadekar if (impl != DENVER_IMPL) { 1711eed3838SVarun Wadekar 1721eed3838SVarun Wadekar /* get the major, minor and sub-version values */ 1731eed3838SVarun Wadekar chip_major = (mmio_read_32(TEGRA_MISC_BASE + 1741eed3838SVarun Wadekar HARDWARE_REVISION_OFFSET) >> 1751eed3838SVarun Wadekar MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK; 1761eed3838SVarun Wadekar chip_minor = (mmio_read_32(TEGRA_MISC_BASE + 1771eed3838SVarun Wadekar HARDWARE_REVISION_OFFSET) >> 1781eed3838SVarun Wadekar MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK; 1791eed3838SVarun Wadekar chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) & 1801eed3838SVarun Wadekar SUBREVISION_MASK; 1811eed3838SVarun Wadekar 1821eed3838SVarun Wadekar /* prepare chip version number */ 1831eed3838SVarun Wadekar val = (chip_major << 12) | (chip_minor << 8) | chip_subrev; 1841eed3838SVarun Wadekar 1851eed3838SVarun Wadekar /* enable L2 ECC for Tegra186 A02P and beyond */ 1861eed3838SVarun Wadekar if (val >= TEGRA186_VER_A02P) { 1871eed3838SVarun Wadekar 1881eed3838SVarun Wadekar val = read_l2ctlr_el1(); 1891eed3838SVarun Wadekar val |= L2_ECC_PARITY_PROTECTION_BIT; 1901eed3838SVarun Wadekar write_l2ctlr_el1(val); 1911eed3838SVarun Wadekar 1921eed3838SVarun Wadekar /* 1931eed3838SVarun Wadekar * Set the flag to enable ECC/Parity Protection 1941eed3838SVarun Wadekar * when we exit System Suspend or Cluster Powerdn 1951eed3838SVarun Wadekar */ 1961eed3838SVarun Wadekar tegra_enable_l2_ecc_parity_prot = 1; 1971eed3838SVarun Wadekar } 1981eed3838SVarun Wadekar } 1991eed3838SVarun Wadekar } 2001eed3838SVarun Wadekar 20150cd8646SVarun Wadekar /* Secure IRQs for Tegra186 */ 20250cd8646SVarun Wadekar static const irq_sec_cfg_t tegra186_sec_irqs[] = { 20350cd8646SVarun Wadekar { 20450cd8646SVarun Wadekar TEGRA186_TOP_WDT_IRQ, 20550cd8646SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 20650cd8646SVarun Wadekar INTR_TYPE_EL3, 20750cd8646SVarun Wadekar }, 20850cd8646SVarun Wadekar { 20950cd8646SVarun Wadekar TEGRA186_AON_WDT_IRQ, 21050cd8646SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 21150cd8646SVarun Wadekar INTR_TYPE_EL3, 21250cd8646SVarun Wadekar }, 21350cd8646SVarun Wadekar }; 21450cd8646SVarun Wadekar 21550cd8646SVarun Wadekar /******************************************************************************* 21650cd8646SVarun Wadekar * Initialize the GIC and SGIs 21750cd8646SVarun Wadekar ******************************************************************************/ 21850cd8646SVarun Wadekar void plat_gic_setup(void) 21950cd8646SVarun Wadekar { 22050cd8646SVarun Wadekar tegra_gic_setup(tegra186_sec_irqs, 22150cd8646SVarun Wadekar sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); 22250cd8646SVarun Wadekar 22350cd8646SVarun Wadekar /* 22450cd8646SVarun Wadekar * Initialize the FIQ handler only if the platform supports any 22550cd8646SVarun Wadekar * FIQ interrupt sources. 22650cd8646SVarun Wadekar */ 22750cd8646SVarun Wadekar if (sizeof(tegra186_sec_irqs) > 0) 22850cd8646SVarun Wadekar tegra_fiq_handler_setup(); 22950cd8646SVarun Wadekar } 23048afb167SVarun Wadekar 23148afb167SVarun Wadekar /******************************************************************************* 23248afb167SVarun Wadekar * Return pointer to the BL31 params from previous bootloader 23348afb167SVarun Wadekar ******************************************************************************/ 23448afb167SVarun Wadekar bl31_params_t *plat_get_bl31_params(void) 23548afb167SVarun Wadekar { 23648afb167SVarun Wadekar uint32_t val; 23748afb167SVarun Wadekar 23848afb167SVarun Wadekar val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); 23948afb167SVarun Wadekar 24048afb167SVarun Wadekar return (bl31_params_t *)(uintptr_t)val; 24148afb167SVarun Wadekar } 24248afb167SVarun Wadekar 24348afb167SVarun Wadekar /******************************************************************************* 24448afb167SVarun Wadekar * Return pointer to the BL31 platform params from previous bootloader 24548afb167SVarun Wadekar ******************************************************************************/ 24648afb167SVarun Wadekar plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 24748afb167SVarun Wadekar { 24848afb167SVarun Wadekar uint32_t val; 24948afb167SVarun Wadekar 25048afb167SVarun Wadekar val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); 25148afb167SVarun Wadekar 25248afb167SVarun Wadekar return (plat_params_from_bl2_t *)(uintptr_t)val; 25348afb167SVarun Wadekar } 254