13cf3183fSVarun Wadekar /* 250402b17SVarun Wadekar * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 53cf3183fSVarun Wadekar */ 63cf3183fSVarun Wadekar 750cd8646SVarun Wadekar #include <arch_helpers.h> 850cd8646SVarun Wadekar #include <assert.h> 948afb167SVarun Wadekar #include <bl31.h> 1050cd8646SVarun Wadekar #include <bl_common.h> 113cf3183fSVarun Wadekar #include <console.h> 1250cd8646SVarun Wadekar #include <context.h> 1350cd8646SVarun Wadekar #include <context_mgmt.h> 141eed3838SVarun Wadekar #include <cortex_a57.h> 1550cd8646SVarun Wadekar #include <debug.h> 1650cd8646SVarun Wadekar #include <denver.h> 1750cd8646SVarun Wadekar #include <interrupt_mgmt.h> 185cb89c56SVarun Wadekar #include <mce.h> 1950cd8646SVarun Wadekar #include <platform.h> 203cf3183fSVarun Wadekar #include <tegra_def.h> 212b04f927SVarun Wadekar #include <tegra_platform.h> 2250cd8646SVarun Wadekar #include <tegra_private.h> 233cf3183fSVarun Wadekar #include <xlat_tables.h> 243cf3183fSVarun Wadekar 251eed3838SVarun Wadekar DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1) 261eed3838SVarun Wadekar extern uint64_t tegra_enable_l2_ecc_parity_prot; 271eed3838SVarun Wadekar 28b67a7c7cSVarun Wadekar /******************************************************************************* 29ae8ac2d2SVarun Wadekar * Tegra186 CPU numbers in cluster #0 30ae8ac2d2SVarun Wadekar ******************************************************************************* 31ae8ac2d2SVarun Wadekar */ 32ae8ac2d2SVarun Wadekar #define TEGRA186_CLUSTER0_CORE2 2 33ae8ac2d2SVarun Wadekar #define TEGRA186_CLUSTER0_CORE3 3 34ae8ac2d2SVarun Wadekar 35ae8ac2d2SVarun Wadekar /******************************************************************************* 36b67a7c7cSVarun Wadekar * The Tegra power domain tree has a single system level power domain i.e. a 37b67a7c7cSVarun Wadekar * single root node. The first entry in the power domain descriptor specifies 38b67a7c7cSVarun Wadekar * the number of power domains at the highest power level. 39b67a7c7cSVarun Wadekar ******************************************************************************* 40b67a7c7cSVarun Wadekar */ 41b67a7c7cSVarun Wadekar const unsigned char tegra_power_domain_tree_desc[] = { 42b67a7c7cSVarun Wadekar /* No of root nodes */ 43b67a7c7cSVarun Wadekar 1, 44b67a7c7cSVarun Wadekar /* No of clusters */ 45b67a7c7cSVarun Wadekar PLATFORM_CLUSTER_COUNT, 46b67a7c7cSVarun Wadekar /* No of CPU cores - cluster0 */ 47b67a7c7cSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER, 48b67a7c7cSVarun Wadekar /* No of CPU cores - cluster1 */ 49b67a7c7cSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER 50b67a7c7cSVarun Wadekar }; 51b67a7c7cSVarun Wadekar 523cf3183fSVarun Wadekar /* 533cf3183fSVarun Wadekar * Table of regions to map using the MMU. 543cf3183fSVarun Wadekar */ 553cf3183fSVarun Wadekar static const mmap_region_t tegra_mmap[] = { 563cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 573cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 58e64ce3abSVarun Wadekar MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 59e64ce3abSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 603cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 613cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 623cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 633cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 6449cbbc4eSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ 6549cbbc4eSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 6649cbbc4eSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ 6749cbbc4eSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 6849cbbc4eSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ 693cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 701eed3838SVarun Wadekar MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ 711eed3838SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 723cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 733cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 7450402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 7550402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 7650402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 7750402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 7850402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 7950402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8067bc721bSVarun Wadekar MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 8167bc721bSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 823cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 833cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8450402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 8550402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 863cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 873cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 88691bc22dSVarun Wadekar MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000, /* 128KB - ARM/Denver */ 89691bc22dSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 90c459206dSPritesh Raithatha MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */ 913cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 923cf3183fSVarun Wadekar {0} 933cf3183fSVarun Wadekar }; 943cf3183fSVarun Wadekar 953cf3183fSVarun Wadekar /******************************************************************************* 963cf3183fSVarun Wadekar * Set up the pagetables as per the platform memory map & initialize the MMU 973cf3183fSVarun Wadekar ******************************************************************************/ 983cf3183fSVarun Wadekar const mmap_region_t *plat_get_mmio_map(void) 993cf3183fSVarun Wadekar { 1003cf3183fSVarun Wadekar /* MMIO space */ 1013cf3183fSVarun Wadekar return tegra_mmap; 1023cf3183fSVarun Wadekar } 1033cf3183fSVarun Wadekar 1043cf3183fSVarun Wadekar /******************************************************************************* 1053cf3183fSVarun Wadekar * Handler to get the System Counter Frequency 1063cf3183fSVarun Wadekar ******************************************************************************/ 1079c2a3d8aSVarun Wadekar unsigned int plat_get_syscnt_freq2(void) 1083cf3183fSVarun Wadekar { 1095d74d68eSVarun Wadekar return 31250000; 1103cf3183fSVarun Wadekar } 1113cf3183fSVarun Wadekar 1123cf3183fSVarun Wadekar /******************************************************************************* 1133cf3183fSVarun Wadekar * Maximum supported UART controllers 1143cf3183fSVarun Wadekar ******************************************************************************/ 1153cf3183fSVarun Wadekar #define TEGRA186_MAX_UART_PORTS 7 1163cf3183fSVarun Wadekar 1173cf3183fSVarun Wadekar /******************************************************************************* 1183cf3183fSVarun Wadekar * This variable holds the UART port base addresses 1193cf3183fSVarun Wadekar ******************************************************************************/ 1203cf3183fSVarun Wadekar static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 1213cf3183fSVarun Wadekar 0, /* undefined - treated as an error case */ 1223cf3183fSVarun Wadekar TEGRA_UARTA_BASE, 1233cf3183fSVarun Wadekar TEGRA_UARTB_BASE, 1243cf3183fSVarun Wadekar TEGRA_UARTC_BASE, 1253cf3183fSVarun Wadekar TEGRA_UARTD_BASE, 1263cf3183fSVarun Wadekar TEGRA_UARTE_BASE, 1273cf3183fSVarun Wadekar TEGRA_UARTF_BASE, 1283cf3183fSVarun Wadekar TEGRA_UARTG_BASE, 1293cf3183fSVarun Wadekar }; 1303cf3183fSVarun Wadekar 1313cf3183fSVarun Wadekar /******************************************************************************* 1323cf3183fSVarun Wadekar * Retrieve the UART controller base to be used as the console 1333cf3183fSVarun Wadekar ******************************************************************************/ 1343cf3183fSVarun Wadekar uint32_t plat_get_console_from_id(int id) 1353cf3183fSVarun Wadekar { 1363cf3183fSVarun Wadekar if (id > TEGRA186_MAX_UART_PORTS) 1373cf3183fSVarun Wadekar return 0; 1383cf3183fSVarun Wadekar 1393cf3183fSVarun Wadekar return tegra186_uart_addresses[id]; 1403cf3183fSVarun Wadekar } 14150cd8646SVarun Wadekar 1421eed3838SVarun Wadekar /* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */ 1431eed3838SVarun Wadekar #define TEGRA186_VER_A02P 0x1201 1441eed3838SVarun Wadekar 1451eed3838SVarun Wadekar /******************************************************************************* 1461eed3838SVarun Wadekar * Handler for early platform setup 1471eed3838SVarun Wadekar ******************************************************************************/ 1481eed3838SVarun Wadekar void plat_early_platform_setup(void) 1491eed3838SVarun Wadekar { 1501eed3838SVarun Wadekar int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 1512b04f927SVarun Wadekar uint32_t chip_subrev, val; 1521eed3838SVarun Wadekar 1531eed3838SVarun Wadekar /* sanity check MCE firmware compatibility */ 1541eed3838SVarun Wadekar mce_verify_firmware_version(); 1551eed3838SVarun Wadekar 1561eed3838SVarun Wadekar /* 1571eed3838SVarun Wadekar * Enable ECC and Parity Protection for Cortex-A57 CPUs 1581eed3838SVarun Wadekar * for Tegra A02p SKUs 1591eed3838SVarun Wadekar */ 1601eed3838SVarun Wadekar if (impl != DENVER_IMPL) { 1611eed3838SVarun Wadekar 1621eed3838SVarun Wadekar /* get the major, minor and sub-version values */ 1631eed3838SVarun Wadekar chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) & 1641eed3838SVarun Wadekar SUBREVISION_MASK; 1651eed3838SVarun Wadekar 1661eed3838SVarun Wadekar /* prepare chip version number */ 1672b04f927SVarun Wadekar val = (tegra_get_chipid_major() << 12) | 1682b04f927SVarun Wadekar (tegra_get_chipid_minor() << 8) | 1692b04f927SVarun Wadekar chip_subrev; 1701eed3838SVarun Wadekar 1711eed3838SVarun Wadekar /* enable L2 ECC for Tegra186 A02P and beyond */ 1721eed3838SVarun Wadekar if (val >= TEGRA186_VER_A02P) { 1731eed3838SVarun Wadekar 1741eed3838SVarun Wadekar val = read_l2ctlr_el1(); 1751eed3838SVarun Wadekar val |= L2_ECC_PARITY_PROTECTION_BIT; 1761eed3838SVarun Wadekar write_l2ctlr_el1(val); 1771eed3838SVarun Wadekar 1781eed3838SVarun Wadekar /* 1791eed3838SVarun Wadekar * Set the flag to enable ECC/Parity Protection 1801eed3838SVarun Wadekar * when we exit System Suspend or Cluster Powerdn 1811eed3838SVarun Wadekar */ 1821eed3838SVarun Wadekar tegra_enable_l2_ecc_parity_prot = 1; 1831eed3838SVarun Wadekar } 1841eed3838SVarun Wadekar } 1851eed3838SVarun Wadekar } 1861eed3838SVarun Wadekar 18750cd8646SVarun Wadekar /* Secure IRQs for Tegra186 */ 18850cd8646SVarun Wadekar static const irq_sec_cfg_t tegra186_sec_irqs[] = { 18950cd8646SVarun Wadekar { 19050cd8646SVarun Wadekar TEGRA186_TOP_WDT_IRQ, 19150cd8646SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 19250cd8646SVarun Wadekar INTR_TYPE_EL3, 19350cd8646SVarun Wadekar }, 19450cd8646SVarun Wadekar { 19550cd8646SVarun Wadekar TEGRA186_AON_WDT_IRQ, 19650cd8646SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 19750cd8646SVarun Wadekar INTR_TYPE_EL3, 19850cd8646SVarun Wadekar }, 19950cd8646SVarun Wadekar }; 20050cd8646SVarun Wadekar 20150cd8646SVarun Wadekar /******************************************************************************* 20250cd8646SVarun Wadekar * Initialize the GIC and SGIs 20350cd8646SVarun Wadekar ******************************************************************************/ 20450cd8646SVarun Wadekar void plat_gic_setup(void) 20550cd8646SVarun Wadekar { 20650cd8646SVarun Wadekar tegra_gic_setup(tegra186_sec_irqs, 20750cd8646SVarun Wadekar sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); 20850cd8646SVarun Wadekar 20950cd8646SVarun Wadekar /* 21050cd8646SVarun Wadekar * Initialize the FIQ handler only if the platform supports any 21150cd8646SVarun Wadekar * FIQ interrupt sources. 21250cd8646SVarun Wadekar */ 21350cd8646SVarun Wadekar if (sizeof(tegra186_sec_irqs) > 0) 21450cd8646SVarun Wadekar tegra_fiq_handler_setup(); 21550cd8646SVarun Wadekar } 21648afb167SVarun Wadekar 21748afb167SVarun Wadekar /******************************************************************************* 21848afb167SVarun Wadekar * Return pointer to the BL31 params from previous bootloader 21948afb167SVarun Wadekar ******************************************************************************/ 22048afb167SVarun Wadekar bl31_params_t *plat_get_bl31_params(void) 22148afb167SVarun Wadekar { 22248afb167SVarun Wadekar uint32_t val; 22348afb167SVarun Wadekar 22448afb167SVarun Wadekar val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); 22548afb167SVarun Wadekar 22648afb167SVarun Wadekar return (bl31_params_t *)(uintptr_t)val; 22748afb167SVarun Wadekar } 22848afb167SVarun Wadekar 22948afb167SVarun Wadekar /******************************************************************************* 23048afb167SVarun Wadekar * Return pointer to the BL31 platform params from previous bootloader 23148afb167SVarun Wadekar ******************************************************************************/ 23248afb167SVarun Wadekar plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 23348afb167SVarun Wadekar { 23448afb167SVarun Wadekar uint32_t val; 23548afb167SVarun Wadekar 23648afb167SVarun Wadekar val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); 23748afb167SVarun Wadekar 23848afb167SVarun Wadekar return (plat_params_from_bl2_t *)(uintptr_t)val; 23948afb167SVarun Wadekar } 240ae8ac2d2SVarun Wadekar 241ae8ac2d2SVarun Wadekar /******************************************************************************* 242ae8ac2d2SVarun Wadekar * This function implements a part of the critical interface between the psci 243ae8ac2d2SVarun Wadekar * generic layer and the platform that allows the former to query the platform 244ae8ac2d2SVarun Wadekar * to convert an MPIDR to a unique linear index. An error code (-1) is returned 245ae8ac2d2SVarun Wadekar * in case the MPIDR is invalid. 246ae8ac2d2SVarun Wadekar ******************************************************************************/ 247ae8ac2d2SVarun Wadekar int plat_core_pos_by_mpidr(u_register_t mpidr) 248ae8ac2d2SVarun Wadekar { 249ae8ac2d2SVarun Wadekar unsigned int cluster_id, cpu_id, pos; 250ae8ac2d2SVarun Wadekar 251ae8ac2d2SVarun Wadekar cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 252ae8ac2d2SVarun Wadekar cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 253ae8ac2d2SVarun Wadekar 254ae8ac2d2SVarun Wadekar /* 255ae8ac2d2SVarun Wadekar * Validate cluster_id by checking whether it represents 256ae8ac2d2SVarun Wadekar * one of the two clusters present on the platform. 257ae8ac2d2SVarun Wadekar */ 258ae8ac2d2SVarun Wadekar if (cluster_id >= PLATFORM_CLUSTER_COUNT) 259ae8ac2d2SVarun Wadekar return PSCI_E_NOT_PRESENT; 260ae8ac2d2SVarun Wadekar 261ae8ac2d2SVarun Wadekar /* 262ae8ac2d2SVarun Wadekar * Validate cpu_id by checking whether it represents a CPU in 263ae8ac2d2SVarun Wadekar * one of the two clusters present on the platform. 264ae8ac2d2SVarun Wadekar */ 265ae8ac2d2SVarun Wadekar if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) 266ae8ac2d2SVarun Wadekar return PSCI_E_NOT_PRESENT; 267ae8ac2d2SVarun Wadekar 268ae8ac2d2SVarun Wadekar /* calculate the core position */ 269ae8ac2d2SVarun Wadekar pos = cpu_id + (cluster_id << 2); 270ae8ac2d2SVarun Wadekar 271ae8ac2d2SVarun Wadekar /* check for non-existent CPUs */ 272ae8ac2d2SVarun Wadekar if (pos == TEGRA186_CLUSTER0_CORE2 || pos == TEGRA186_CLUSTER0_CORE3) 273ae8ac2d2SVarun Wadekar return PSCI_E_NOT_PRESENT; 274ae8ac2d2SVarun Wadekar 275ae8ac2d2SVarun Wadekar return pos; 276ae8ac2d2SVarun Wadekar } 277