13cf3183fSVarun Wadekar /* 2*80c50eeaSVarun Wadekar * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 53cf3183fSVarun Wadekar */ 63cf3183fSVarun Wadekar 750cd8646SVarun Wadekar #include <arch_helpers.h> 850cd8646SVarun Wadekar #include <assert.h> 948afb167SVarun Wadekar #include <bl31.h> 1050cd8646SVarun Wadekar #include <bl_common.h> 113cf3183fSVarun Wadekar #include <console.h> 1250cd8646SVarun Wadekar #include <context.h> 1350cd8646SVarun Wadekar #include <context_mgmt.h> 141eed3838SVarun Wadekar #include <cortex_a57.h> 1550cd8646SVarun Wadekar #include <debug.h> 1650cd8646SVarun Wadekar #include <denver.h> 17*80c50eeaSVarun Wadekar #include <gic_common.h> 18*80c50eeaSVarun Wadekar #include <gicv2.h> 1950cd8646SVarun Wadekar #include <interrupt_mgmt.h> 20*80c50eeaSVarun Wadekar #include <interrupt_props.h> 215cb89c56SVarun Wadekar #include <mce.h> 2250cd8646SVarun Wadekar #include <platform.h> 233cf3183fSVarun Wadekar #include <tegra_def.h> 242b04f927SVarun Wadekar #include <tegra_platform.h> 2550cd8646SVarun Wadekar #include <tegra_private.h> 2628db3e96SAndreas Färber #include <xlat_tables_v2.h> 273cf3183fSVarun Wadekar 28fb7d32e5SVarun Wadekar DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1) 291eed3838SVarun Wadekar extern uint64_t tegra_enable_l2_ecc_parity_prot; 301eed3838SVarun Wadekar 31b67a7c7cSVarun Wadekar /******************************************************************************* 32ae8ac2d2SVarun Wadekar * Tegra186 CPU numbers in cluster #0 33ae8ac2d2SVarun Wadekar ******************************************************************************* 34ae8ac2d2SVarun Wadekar */ 35ae8ac2d2SVarun Wadekar #define TEGRA186_CLUSTER0_CORE2 2 36ae8ac2d2SVarun Wadekar #define TEGRA186_CLUSTER0_CORE3 3 37ae8ac2d2SVarun Wadekar 38ae8ac2d2SVarun Wadekar /******************************************************************************* 39b67a7c7cSVarun Wadekar * The Tegra power domain tree has a single system level power domain i.e. a 40b67a7c7cSVarun Wadekar * single root node. The first entry in the power domain descriptor specifies 41b67a7c7cSVarun Wadekar * the number of power domains at the highest power level. 42b67a7c7cSVarun Wadekar ******************************************************************************* 43b67a7c7cSVarun Wadekar */ 44b67a7c7cSVarun Wadekar const unsigned char tegra_power_domain_tree_desc[] = { 45b67a7c7cSVarun Wadekar /* No of root nodes */ 46b67a7c7cSVarun Wadekar 1, 47b67a7c7cSVarun Wadekar /* No of clusters */ 48b67a7c7cSVarun Wadekar PLATFORM_CLUSTER_COUNT, 49b67a7c7cSVarun Wadekar /* No of CPU cores - cluster0 */ 50b67a7c7cSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER, 51b67a7c7cSVarun Wadekar /* No of CPU cores - cluster1 */ 52b67a7c7cSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER 53b67a7c7cSVarun Wadekar }; 54b67a7c7cSVarun Wadekar 553cf3183fSVarun Wadekar /* 563cf3183fSVarun Wadekar * Table of regions to map using the MMU. 573cf3183fSVarun Wadekar */ 583cf3183fSVarun Wadekar static const mmap_region_t tegra_mmap[] = { 593cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 603cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 61e64ce3abSVarun Wadekar MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 62e64ce3abSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 633cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 643cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 653cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 663cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 6749cbbc4eSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ 6849cbbc4eSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 6949cbbc4eSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ 7049cbbc4eSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 7149cbbc4eSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ 723cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 731eed3838SVarun Wadekar MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ 741eed3838SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 753cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 763cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 7750402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 7850402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 7950402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 8050402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8150402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 8250402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8367bc721bSVarun Wadekar MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 8467bc721bSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 853cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 863cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8750402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 8850402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 893cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 903cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 91691bc22dSVarun Wadekar MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000, /* 128KB - ARM/Denver */ 92691bc22dSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 93c459206dSPritesh Raithatha MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */ 943cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 953cf3183fSVarun Wadekar {0} 963cf3183fSVarun Wadekar }; 973cf3183fSVarun Wadekar 983cf3183fSVarun Wadekar /******************************************************************************* 993cf3183fSVarun Wadekar * Set up the pagetables as per the platform memory map & initialize the MMU 1003cf3183fSVarun Wadekar ******************************************************************************/ 1013cf3183fSVarun Wadekar const mmap_region_t *plat_get_mmio_map(void) 1023cf3183fSVarun Wadekar { 1033cf3183fSVarun Wadekar /* MMIO space */ 1043cf3183fSVarun Wadekar return tegra_mmap; 1053cf3183fSVarun Wadekar } 1063cf3183fSVarun Wadekar 1073cf3183fSVarun Wadekar /******************************************************************************* 1083cf3183fSVarun Wadekar * Handler to get the System Counter Frequency 1093cf3183fSVarun Wadekar ******************************************************************************/ 1109c2a3d8aSVarun Wadekar unsigned int plat_get_syscnt_freq2(void) 1113cf3183fSVarun Wadekar { 1125d74d68eSVarun Wadekar return 31250000; 1133cf3183fSVarun Wadekar } 1143cf3183fSVarun Wadekar 1153cf3183fSVarun Wadekar /******************************************************************************* 1163cf3183fSVarun Wadekar * Maximum supported UART controllers 1173cf3183fSVarun Wadekar ******************************************************************************/ 1183cf3183fSVarun Wadekar #define TEGRA186_MAX_UART_PORTS 7 1193cf3183fSVarun Wadekar 1203cf3183fSVarun Wadekar /******************************************************************************* 1213cf3183fSVarun Wadekar * This variable holds the UART port base addresses 1223cf3183fSVarun Wadekar ******************************************************************************/ 1233cf3183fSVarun Wadekar static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 1243cf3183fSVarun Wadekar 0, /* undefined - treated as an error case */ 1253cf3183fSVarun Wadekar TEGRA_UARTA_BASE, 1263cf3183fSVarun Wadekar TEGRA_UARTB_BASE, 1273cf3183fSVarun Wadekar TEGRA_UARTC_BASE, 1283cf3183fSVarun Wadekar TEGRA_UARTD_BASE, 1293cf3183fSVarun Wadekar TEGRA_UARTE_BASE, 1303cf3183fSVarun Wadekar TEGRA_UARTF_BASE, 1313cf3183fSVarun Wadekar TEGRA_UARTG_BASE, 1323cf3183fSVarun Wadekar }; 1333cf3183fSVarun Wadekar 1343cf3183fSVarun Wadekar /******************************************************************************* 1353cf3183fSVarun Wadekar * Retrieve the UART controller base to be used as the console 1363cf3183fSVarun Wadekar ******************************************************************************/ 1373cf3183fSVarun Wadekar uint32_t plat_get_console_from_id(int id) 1383cf3183fSVarun Wadekar { 1393cf3183fSVarun Wadekar if (id > TEGRA186_MAX_UART_PORTS) 1403cf3183fSVarun Wadekar return 0; 1413cf3183fSVarun Wadekar 1423cf3183fSVarun Wadekar return tegra186_uart_addresses[id]; 1433cf3183fSVarun Wadekar } 14450cd8646SVarun Wadekar 1451eed3838SVarun Wadekar /* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */ 1461eed3838SVarun Wadekar #define TEGRA186_VER_A02P 0x1201 1471eed3838SVarun Wadekar 1481eed3838SVarun Wadekar /******************************************************************************* 1491eed3838SVarun Wadekar * Handler for early platform setup 1501eed3838SVarun Wadekar ******************************************************************************/ 1511eed3838SVarun Wadekar void plat_early_platform_setup(void) 1521eed3838SVarun Wadekar { 1531eed3838SVarun Wadekar int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 1542b04f927SVarun Wadekar uint32_t chip_subrev, val; 1551eed3838SVarun Wadekar 1561eed3838SVarun Wadekar /* sanity check MCE firmware compatibility */ 1571eed3838SVarun Wadekar mce_verify_firmware_version(); 1581eed3838SVarun Wadekar 1591eed3838SVarun Wadekar /* 1601eed3838SVarun Wadekar * Enable ECC and Parity Protection for Cortex-A57 CPUs 1611eed3838SVarun Wadekar * for Tegra A02p SKUs 1621eed3838SVarun Wadekar */ 1631eed3838SVarun Wadekar if (impl != DENVER_IMPL) { 1641eed3838SVarun Wadekar 1651eed3838SVarun Wadekar /* get the major, minor and sub-version values */ 1661eed3838SVarun Wadekar chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) & 1671eed3838SVarun Wadekar SUBREVISION_MASK; 1681eed3838SVarun Wadekar 1691eed3838SVarun Wadekar /* prepare chip version number */ 1702b04f927SVarun Wadekar val = (tegra_get_chipid_major() << 12) | 1712b04f927SVarun Wadekar (tegra_get_chipid_minor() << 8) | 1722b04f927SVarun Wadekar chip_subrev; 1731eed3838SVarun Wadekar 1741eed3838SVarun Wadekar /* enable L2 ECC for Tegra186 A02P and beyond */ 1751eed3838SVarun Wadekar if (val >= TEGRA186_VER_A02P) { 1761eed3838SVarun Wadekar 1771eed3838SVarun Wadekar val = read_l2ctlr_el1(); 178fb7d32e5SVarun Wadekar val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; 1791eed3838SVarun Wadekar write_l2ctlr_el1(val); 1801eed3838SVarun Wadekar 1811eed3838SVarun Wadekar /* 1821eed3838SVarun Wadekar * Set the flag to enable ECC/Parity Protection 1831eed3838SVarun Wadekar * when we exit System Suspend or Cluster Powerdn 1841eed3838SVarun Wadekar */ 1851eed3838SVarun Wadekar tegra_enable_l2_ecc_parity_prot = 1; 1861eed3838SVarun Wadekar } 1871eed3838SVarun Wadekar } 1881eed3838SVarun Wadekar } 1891eed3838SVarun Wadekar 19050cd8646SVarun Wadekar /* Secure IRQs for Tegra186 */ 191*80c50eeaSVarun Wadekar static const interrupt_prop_t tegra186_interrupt_props[] = { 192*80c50eeaSVarun Wadekar INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 193*80c50eeaSVarun Wadekar GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 194*80c50eeaSVarun Wadekar INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 195*80c50eeaSVarun Wadekar GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE) 19650cd8646SVarun Wadekar }; 19750cd8646SVarun Wadekar 19850cd8646SVarun Wadekar /******************************************************************************* 19950cd8646SVarun Wadekar * Initialize the GIC and SGIs 20050cd8646SVarun Wadekar ******************************************************************************/ 20150cd8646SVarun Wadekar void plat_gic_setup(void) 20250cd8646SVarun Wadekar { 203*80c50eeaSVarun Wadekar tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props)); 20450cd8646SVarun Wadekar 20550cd8646SVarun Wadekar /* 20650cd8646SVarun Wadekar * Initialize the FIQ handler only if the platform supports any 20750cd8646SVarun Wadekar * FIQ interrupt sources. 20850cd8646SVarun Wadekar */ 209*80c50eeaSVarun Wadekar if (sizeof(tegra186_interrupt_props) > 0) 21050cd8646SVarun Wadekar tegra_fiq_handler_setup(); 21150cd8646SVarun Wadekar } 21248afb167SVarun Wadekar 21348afb167SVarun Wadekar /******************************************************************************* 21448afb167SVarun Wadekar * Return pointer to the BL31 params from previous bootloader 21548afb167SVarun Wadekar ******************************************************************************/ 216fdcc1127SAntonio Nino Diaz struct tegra_bl31_params *plat_get_bl31_params(void) 21748afb167SVarun Wadekar { 21848afb167SVarun Wadekar uint32_t val; 21948afb167SVarun Wadekar 22048afb167SVarun Wadekar val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); 22148afb167SVarun Wadekar 222fdcc1127SAntonio Nino Diaz return (struct tegra_bl31_params *)(uintptr_t)val; 22348afb167SVarun Wadekar } 22448afb167SVarun Wadekar 22548afb167SVarun Wadekar /******************************************************************************* 22648afb167SVarun Wadekar * Return pointer to the BL31 platform params from previous bootloader 22748afb167SVarun Wadekar ******************************************************************************/ 22848afb167SVarun Wadekar plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 22948afb167SVarun Wadekar { 23048afb167SVarun Wadekar uint32_t val; 23148afb167SVarun Wadekar 23248afb167SVarun Wadekar val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); 23348afb167SVarun Wadekar 23448afb167SVarun Wadekar return (plat_params_from_bl2_t *)(uintptr_t)val; 23548afb167SVarun Wadekar } 236ae8ac2d2SVarun Wadekar 237ae8ac2d2SVarun Wadekar /******************************************************************************* 238ae8ac2d2SVarun Wadekar * This function implements a part of the critical interface between the psci 239ae8ac2d2SVarun Wadekar * generic layer and the platform that allows the former to query the platform 240ae8ac2d2SVarun Wadekar * to convert an MPIDR to a unique linear index. An error code (-1) is returned 241ae8ac2d2SVarun Wadekar * in case the MPIDR is invalid. 242ae8ac2d2SVarun Wadekar ******************************************************************************/ 243ae8ac2d2SVarun Wadekar int plat_core_pos_by_mpidr(u_register_t mpidr) 244ae8ac2d2SVarun Wadekar { 245ae8ac2d2SVarun Wadekar unsigned int cluster_id, cpu_id, pos; 246ae8ac2d2SVarun Wadekar 247ae8ac2d2SVarun Wadekar cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 248ae8ac2d2SVarun Wadekar cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 249ae8ac2d2SVarun Wadekar 250ae8ac2d2SVarun Wadekar /* 251ae8ac2d2SVarun Wadekar * Validate cluster_id by checking whether it represents 252ae8ac2d2SVarun Wadekar * one of the two clusters present on the platform. 253ae8ac2d2SVarun Wadekar */ 254ae8ac2d2SVarun Wadekar if (cluster_id >= PLATFORM_CLUSTER_COUNT) 255ae8ac2d2SVarun Wadekar return PSCI_E_NOT_PRESENT; 256ae8ac2d2SVarun Wadekar 257ae8ac2d2SVarun Wadekar /* 258ae8ac2d2SVarun Wadekar * Validate cpu_id by checking whether it represents a CPU in 259ae8ac2d2SVarun Wadekar * one of the two clusters present on the platform. 260ae8ac2d2SVarun Wadekar */ 261ae8ac2d2SVarun Wadekar if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) 262ae8ac2d2SVarun Wadekar return PSCI_E_NOT_PRESENT; 263ae8ac2d2SVarun Wadekar 264ae8ac2d2SVarun Wadekar /* calculate the core position */ 265ae8ac2d2SVarun Wadekar pos = cpu_id + (cluster_id << 2); 266ae8ac2d2SVarun Wadekar 267ae8ac2d2SVarun Wadekar /* check for non-existent CPUs */ 268ae8ac2d2SVarun Wadekar if (pos == TEGRA186_CLUSTER0_CORE2 || pos == TEGRA186_CLUSTER0_CORE3) 269ae8ac2d2SVarun Wadekar return PSCI_E_NOT_PRESENT; 270ae8ac2d2SVarun Wadekar 271ae8ac2d2SVarun Wadekar return pos; 272ae8ac2d2SVarun Wadekar } 273