13cf3183fSVarun Wadekar /* 280c50eeaSVarun Wadekar * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 53cf3183fSVarun Wadekar */ 63cf3183fSVarun Wadekar 750cd8646SVarun Wadekar #include <assert.h> 809d40e0eSAntonio Nino Diaz 909d40e0eSAntonio Nino Diaz #include <arch_helpers.h> 1009d40e0eSAntonio Nino Diaz #include <bl31/bl31.h> 1109d40e0eSAntonio Nino Diaz #include <bl31/interrupt_mgmt.h> 1209d40e0eSAntonio Nino Diaz #include <common/bl_common.h> 1309d40e0eSAntonio Nino Diaz #include <common/debug.h> 1409d40e0eSAntonio Nino Diaz #include <common/interrupt_props.h> 1550cd8646SVarun Wadekar #include <context.h> 161eed3838SVarun Wadekar #include <cortex_a57.h> 1750cd8646SVarun Wadekar #include <denver.h> 1809d40e0eSAntonio Nino Diaz #include <drivers/arm/gic_common.h> 1909d40e0eSAntonio Nino Diaz #include <drivers/arm/gicv2.h> 2009d40e0eSAntonio Nino Diaz #include <drivers/console.h> 2109d40e0eSAntonio Nino Diaz #include <lib/el3_runtime/context_mgmt.h> 2209d40e0eSAntonio Nino Diaz #include <lib/xlat_tables/xlat_tables_v2.h> 2309d40e0eSAntonio Nino Diaz #include <plat/common/platform.h> 2409d40e0eSAntonio Nino Diaz 255cb89c56SVarun Wadekar #include <mce.h> 263cf3183fSVarun Wadekar #include <tegra_def.h> 272b04f927SVarun Wadekar #include <tegra_platform.h> 2850cd8646SVarun Wadekar #include <tegra_private.h> 293cf3183fSVarun Wadekar 30fb7d32e5SVarun Wadekar DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1) 311eed3838SVarun Wadekar extern uint64_t tegra_enable_l2_ecc_parity_prot; 321eed3838SVarun Wadekar 33b67a7c7cSVarun Wadekar /******************************************************************************* 34ae8ac2d2SVarun Wadekar * Tegra186 CPU numbers in cluster #0 35ae8ac2d2SVarun Wadekar ******************************************************************************* 36ae8ac2d2SVarun Wadekar */ 37ae8ac2d2SVarun Wadekar #define TEGRA186_CLUSTER0_CORE2 2 38ae8ac2d2SVarun Wadekar #define TEGRA186_CLUSTER0_CORE3 3 39ae8ac2d2SVarun Wadekar 40ae8ac2d2SVarun Wadekar /******************************************************************************* 41b67a7c7cSVarun Wadekar * The Tegra power domain tree has a single system level power domain i.e. a 42b67a7c7cSVarun Wadekar * single root node. The first entry in the power domain descriptor specifies 43b67a7c7cSVarun Wadekar * the number of power domains at the highest power level. 44b67a7c7cSVarun Wadekar ******************************************************************************* 45b67a7c7cSVarun Wadekar */ 46b67a7c7cSVarun Wadekar const unsigned char tegra_power_domain_tree_desc[] = { 47b67a7c7cSVarun Wadekar /* No of root nodes */ 48b67a7c7cSVarun Wadekar 1, 49b67a7c7cSVarun Wadekar /* No of clusters */ 50b67a7c7cSVarun Wadekar PLATFORM_CLUSTER_COUNT, 51b67a7c7cSVarun Wadekar /* No of CPU cores - cluster0 */ 52b67a7c7cSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER, 53b67a7c7cSVarun Wadekar /* No of CPU cores - cluster1 */ 54b67a7c7cSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER 55b67a7c7cSVarun Wadekar }; 56b67a7c7cSVarun Wadekar 57*7b3b41d6SVarun Wadekar /******************************************************************************* 58*7b3b41d6SVarun Wadekar * This function returns the Tegra default topology tree information. 59*7b3b41d6SVarun Wadekar ******************************************************************************/ 60*7b3b41d6SVarun Wadekar const unsigned char *plat_get_power_domain_tree_desc(void) 61*7b3b41d6SVarun Wadekar { 62*7b3b41d6SVarun Wadekar return tegra_power_domain_tree_desc; 63*7b3b41d6SVarun Wadekar } 64*7b3b41d6SVarun Wadekar 653cf3183fSVarun Wadekar /* 663cf3183fSVarun Wadekar * Table of regions to map using the MMU. 673cf3183fSVarun Wadekar */ 683cf3183fSVarun Wadekar static const mmap_region_t tegra_mmap[] = { 693cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 703cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 71e64ce3abSVarun Wadekar MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 72e64ce3abSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 733cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 743cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 753cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 763cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 7749cbbc4eSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ 7849cbbc4eSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 7949cbbc4eSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ 8049cbbc4eSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8149cbbc4eSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ 823cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 831eed3838SVarun Wadekar MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ 841eed3838SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 853cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 863cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8750402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 8850402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 8950402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 9050402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 9150402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 9250402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 9367bc721bSVarun Wadekar MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 9467bc721bSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 953cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 963cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 9750402b17SVarun Wadekar MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 9850402b17SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 993cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 1003cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 101691bc22dSVarun Wadekar MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000, /* 128KB - ARM/Denver */ 102691bc22dSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 103c459206dSPritesh Raithatha MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */ 1043cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 1053cf3183fSVarun Wadekar {0} 1063cf3183fSVarun Wadekar }; 1073cf3183fSVarun Wadekar 1083cf3183fSVarun Wadekar /******************************************************************************* 1093cf3183fSVarun Wadekar * Set up the pagetables as per the platform memory map & initialize the MMU 1103cf3183fSVarun Wadekar ******************************************************************************/ 1113cf3183fSVarun Wadekar const mmap_region_t *plat_get_mmio_map(void) 1123cf3183fSVarun Wadekar { 1133cf3183fSVarun Wadekar /* MMIO space */ 1143cf3183fSVarun Wadekar return tegra_mmap; 1153cf3183fSVarun Wadekar } 1163cf3183fSVarun Wadekar 1173cf3183fSVarun Wadekar /******************************************************************************* 1183cf3183fSVarun Wadekar * Handler to get the System Counter Frequency 1193cf3183fSVarun Wadekar ******************************************************************************/ 1209c2a3d8aSVarun Wadekar unsigned int plat_get_syscnt_freq2(void) 1213cf3183fSVarun Wadekar { 1225d74d68eSVarun Wadekar return 31250000; 1233cf3183fSVarun Wadekar } 1243cf3183fSVarun Wadekar 1253cf3183fSVarun Wadekar /******************************************************************************* 1263cf3183fSVarun Wadekar * Maximum supported UART controllers 1273cf3183fSVarun Wadekar ******************************************************************************/ 1283cf3183fSVarun Wadekar #define TEGRA186_MAX_UART_PORTS 7 1293cf3183fSVarun Wadekar 1303cf3183fSVarun Wadekar /******************************************************************************* 1313cf3183fSVarun Wadekar * This variable holds the UART port base addresses 1323cf3183fSVarun Wadekar ******************************************************************************/ 1333cf3183fSVarun Wadekar static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 1343cf3183fSVarun Wadekar 0, /* undefined - treated as an error case */ 1353cf3183fSVarun Wadekar TEGRA_UARTA_BASE, 1363cf3183fSVarun Wadekar TEGRA_UARTB_BASE, 1373cf3183fSVarun Wadekar TEGRA_UARTC_BASE, 1383cf3183fSVarun Wadekar TEGRA_UARTD_BASE, 1393cf3183fSVarun Wadekar TEGRA_UARTE_BASE, 1403cf3183fSVarun Wadekar TEGRA_UARTF_BASE, 1413cf3183fSVarun Wadekar TEGRA_UARTG_BASE, 1423cf3183fSVarun Wadekar }; 1433cf3183fSVarun Wadekar 1443cf3183fSVarun Wadekar /******************************************************************************* 1453cf3183fSVarun Wadekar * Retrieve the UART controller base to be used as the console 1463cf3183fSVarun Wadekar ******************************************************************************/ 1473cf3183fSVarun Wadekar uint32_t plat_get_console_from_id(int id) 1483cf3183fSVarun Wadekar { 1493cf3183fSVarun Wadekar if (id > TEGRA186_MAX_UART_PORTS) 1503cf3183fSVarun Wadekar return 0; 1513cf3183fSVarun Wadekar 1523cf3183fSVarun Wadekar return tegra186_uart_addresses[id]; 1533cf3183fSVarun Wadekar } 15450cd8646SVarun Wadekar 1551eed3838SVarun Wadekar /* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */ 1561eed3838SVarun Wadekar #define TEGRA186_VER_A02P 0x1201 1571eed3838SVarun Wadekar 1581eed3838SVarun Wadekar /******************************************************************************* 1591eed3838SVarun Wadekar * Handler for early platform setup 1601eed3838SVarun Wadekar ******************************************************************************/ 1611eed3838SVarun Wadekar void plat_early_platform_setup(void) 1621eed3838SVarun Wadekar { 1631eed3838SVarun Wadekar int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 1642b04f927SVarun Wadekar uint32_t chip_subrev, val; 1651eed3838SVarun Wadekar 1661eed3838SVarun Wadekar /* sanity check MCE firmware compatibility */ 1671eed3838SVarun Wadekar mce_verify_firmware_version(); 1681eed3838SVarun Wadekar 1691eed3838SVarun Wadekar /* 1701eed3838SVarun Wadekar * Enable ECC and Parity Protection for Cortex-A57 CPUs 1711eed3838SVarun Wadekar * for Tegra A02p SKUs 1721eed3838SVarun Wadekar */ 1731eed3838SVarun Wadekar if (impl != DENVER_IMPL) { 1741eed3838SVarun Wadekar 1751eed3838SVarun Wadekar /* get the major, minor and sub-version values */ 1761eed3838SVarun Wadekar chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) & 1771eed3838SVarun Wadekar SUBREVISION_MASK; 1781eed3838SVarun Wadekar 1791eed3838SVarun Wadekar /* prepare chip version number */ 1802b04f927SVarun Wadekar val = (tegra_get_chipid_major() << 12) | 1812b04f927SVarun Wadekar (tegra_get_chipid_minor() << 8) | 1822b04f927SVarun Wadekar chip_subrev; 1831eed3838SVarun Wadekar 1841eed3838SVarun Wadekar /* enable L2 ECC for Tegra186 A02P and beyond */ 1851eed3838SVarun Wadekar if (val >= TEGRA186_VER_A02P) { 1861eed3838SVarun Wadekar 1871eed3838SVarun Wadekar val = read_l2ctlr_el1(); 188fb7d32e5SVarun Wadekar val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; 1891eed3838SVarun Wadekar write_l2ctlr_el1(val); 1901eed3838SVarun Wadekar 1911eed3838SVarun Wadekar /* 1921eed3838SVarun Wadekar * Set the flag to enable ECC/Parity Protection 1931eed3838SVarun Wadekar * when we exit System Suspend or Cluster Powerdn 1941eed3838SVarun Wadekar */ 1951eed3838SVarun Wadekar tegra_enable_l2_ecc_parity_prot = 1; 1961eed3838SVarun Wadekar } 1971eed3838SVarun Wadekar } 1981eed3838SVarun Wadekar } 1991eed3838SVarun Wadekar 20050cd8646SVarun Wadekar /* Secure IRQs for Tegra186 */ 20180c50eeaSVarun Wadekar static const interrupt_prop_t tegra186_interrupt_props[] = { 20280c50eeaSVarun Wadekar INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 20380c50eeaSVarun Wadekar GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 20480c50eeaSVarun Wadekar INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 20580c50eeaSVarun Wadekar GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE) 20650cd8646SVarun Wadekar }; 20750cd8646SVarun Wadekar 20850cd8646SVarun Wadekar /******************************************************************************* 20950cd8646SVarun Wadekar * Initialize the GIC and SGIs 21050cd8646SVarun Wadekar ******************************************************************************/ 21150cd8646SVarun Wadekar void plat_gic_setup(void) 21250cd8646SVarun Wadekar { 21380c50eeaSVarun Wadekar tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props)); 21450cd8646SVarun Wadekar 21550cd8646SVarun Wadekar /* 21650cd8646SVarun Wadekar * Initialize the FIQ handler only if the platform supports any 21750cd8646SVarun Wadekar * FIQ interrupt sources. 21850cd8646SVarun Wadekar */ 21980c50eeaSVarun Wadekar if (sizeof(tegra186_interrupt_props) > 0) 22050cd8646SVarun Wadekar tegra_fiq_handler_setup(); 22150cd8646SVarun Wadekar } 22248afb167SVarun Wadekar 22348afb167SVarun Wadekar /******************************************************************************* 22448afb167SVarun Wadekar * Return pointer to the BL31 params from previous bootloader 22548afb167SVarun Wadekar ******************************************************************************/ 226fdcc1127SAntonio Nino Diaz struct tegra_bl31_params *plat_get_bl31_params(void) 22748afb167SVarun Wadekar { 22848afb167SVarun Wadekar uint32_t val; 22948afb167SVarun Wadekar 23048afb167SVarun Wadekar val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); 23148afb167SVarun Wadekar 232fdcc1127SAntonio Nino Diaz return (struct tegra_bl31_params *)(uintptr_t)val; 23348afb167SVarun Wadekar } 23448afb167SVarun Wadekar 23548afb167SVarun Wadekar /******************************************************************************* 23648afb167SVarun Wadekar * Return pointer to the BL31 platform params from previous bootloader 23748afb167SVarun Wadekar ******************************************************************************/ 23848afb167SVarun Wadekar plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 23948afb167SVarun Wadekar { 24048afb167SVarun Wadekar uint32_t val; 24148afb167SVarun Wadekar 24248afb167SVarun Wadekar val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); 24348afb167SVarun Wadekar 24448afb167SVarun Wadekar return (plat_params_from_bl2_t *)(uintptr_t)val; 24548afb167SVarun Wadekar } 246ae8ac2d2SVarun Wadekar 247ae8ac2d2SVarun Wadekar /******************************************************************************* 248ae8ac2d2SVarun Wadekar * This function implements a part of the critical interface between the psci 249ae8ac2d2SVarun Wadekar * generic layer and the platform that allows the former to query the platform 250ae8ac2d2SVarun Wadekar * to convert an MPIDR to a unique linear index. An error code (-1) is returned 251ae8ac2d2SVarun Wadekar * in case the MPIDR is invalid. 252ae8ac2d2SVarun Wadekar ******************************************************************************/ 253ae8ac2d2SVarun Wadekar int plat_core_pos_by_mpidr(u_register_t mpidr) 254ae8ac2d2SVarun Wadekar { 255ae8ac2d2SVarun Wadekar unsigned int cluster_id, cpu_id, pos; 256ae8ac2d2SVarun Wadekar 257ae8ac2d2SVarun Wadekar cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 258ae8ac2d2SVarun Wadekar cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 259ae8ac2d2SVarun Wadekar 260ae8ac2d2SVarun Wadekar /* 261ae8ac2d2SVarun Wadekar * Validate cluster_id by checking whether it represents 262ae8ac2d2SVarun Wadekar * one of the two clusters present on the platform. 263ae8ac2d2SVarun Wadekar */ 264ae8ac2d2SVarun Wadekar if (cluster_id >= PLATFORM_CLUSTER_COUNT) 265ae8ac2d2SVarun Wadekar return PSCI_E_NOT_PRESENT; 266ae8ac2d2SVarun Wadekar 267ae8ac2d2SVarun Wadekar /* 268ae8ac2d2SVarun Wadekar * Validate cpu_id by checking whether it represents a CPU in 269ae8ac2d2SVarun Wadekar * one of the two clusters present on the platform. 270ae8ac2d2SVarun Wadekar */ 271ae8ac2d2SVarun Wadekar if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) 272ae8ac2d2SVarun Wadekar return PSCI_E_NOT_PRESENT; 273ae8ac2d2SVarun Wadekar 274ae8ac2d2SVarun Wadekar /* calculate the core position */ 275ae8ac2d2SVarun Wadekar pos = cpu_id + (cluster_id << 2); 276ae8ac2d2SVarun Wadekar 277ae8ac2d2SVarun Wadekar /* check for non-existent CPUs */ 278ae8ac2d2SVarun Wadekar if (pos == TEGRA186_CLUSTER0_CORE2 || pos == TEGRA186_CLUSTER0_CORE3) 279ae8ac2d2SVarun Wadekar return PSCI_E_NOT_PRESENT; 280ae8ac2d2SVarun Wadekar 281ae8ac2d2SVarun Wadekar return pos; 282ae8ac2d2SVarun Wadekar } 283