xref: /rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/plat_setup.c (revision 5d74d68e52659b5f4eba5bb8a35d96979f19e0c9)
13cf3183fSVarun Wadekar /*
23cf3183fSVarun Wadekar  * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
33cf3183fSVarun Wadekar  *
43cf3183fSVarun Wadekar  * Redistribution and use in source and binary forms, with or without
53cf3183fSVarun Wadekar  * modification, are permitted provided that the following conditions are met:
63cf3183fSVarun Wadekar  *
73cf3183fSVarun Wadekar  * Redistributions of source code must retain the above copyright notice, this
83cf3183fSVarun Wadekar  * list of conditions and the following disclaimer.
93cf3183fSVarun Wadekar  *
103cf3183fSVarun Wadekar  * Redistributions in binary form must reproduce the above copyright notice,
113cf3183fSVarun Wadekar  * this list of conditions and the following disclaimer in the documentation
123cf3183fSVarun Wadekar  * and/or other materials provided with the distribution.
133cf3183fSVarun Wadekar  *
143cf3183fSVarun Wadekar  * Neither the name of ARM nor the names of its contributors may be used
153cf3183fSVarun Wadekar  * to endorse or promote products derived from this software without specific
163cf3183fSVarun Wadekar  * prior written permission.
173cf3183fSVarun Wadekar  *
183cf3183fSVarun Wadekar  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
193cf3183fSVarun Wadekar  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
203cf3183fSVarun Wadekar  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
213cf3183fSVarun Wadekar  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
223cf3183fSVarun Wadekar  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
233cf3183fSVarun Wadekar  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
243cf3183fSVarun Wadekar  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
253cf3183fSVarun Wadekar  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
263cf3183fSVarun Wadekar  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
273cf3183fSVarun Wadekar  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
283cf3183fSVarun Wadekar  * POSSIBILITY OF SUCH DAMAGE.
293cf3183fSVarun Wadekar  */
303cf3183fSVarun Wadekar 
313cf3183fSVarun Wadekar #include <console.h>
323cf3183fSVarun Wadekar #include <tegra_def.h>
333cf3183fSVarun Wadekar #include <xlat_tables.h>
343cf3183fSVarun Wadekar 
353cf3183fSVarun Wadekar /*
363cf3183fSVarun Wadekar  * Table of regions to map using the MMU.
373cf3183fSVarun Wadekar  */
383cf3183fSVarun Wadekar static const mmap_region_t tegra_mmap[] = {
393cf3183fSVarun Wadekar 	MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */
403cf3183fSVarun Wadekar 			MT_DEVICE | MT_RW | MT_SECURE),
413cf3183fSVarun Wadekar 	MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */
423cf3183fSVarun Wadekar 			MT_DEVICE | MT_RW | MT_SECURE),
433cf3183fSVarun Wadekar 	MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */
443cf3183fSVarun Wadekar 			MT_DEVICE | MT_RW | MT_SECURE),
453cf3183fSVarun Wadekar 	MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB */
463cf3183fSVarun Wadekar 			MT_DEVICE | MT_RW | MT_SECURE),
473cf3183fSVarun Wadekar 	MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */
483cf3183fSVarun Wadekar 			MT_DEVICE | MT_RW | MT_SECURE),
493cf3183fSVarun Wadekar 	MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */
503cf3183fSVarun Wadekar 			MT_DEVICE | MT_RW | MT_SECURE),
513cf3183fSVarun Wadekar 	MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
523cf3183fSVarun Wadekar 			MT_DEVICE | MT_RW | MT_SECURE),
533cf3183fSVarun Wadekar 	MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x10000, /* 64KB */
543cf3183fSVarun Wadekar 			MT_DEVICE | MT_RW | MT_SECURE),
553cf3183fSVarun Wadekar 	{0}
563cf3183fSVarun Wadekar };
573cf3183fSVarun Wadekar 
583cf3183fSVarun Wadekar /*******************************************************************************
593cf3183fSVarun Wadekar  * Set up the pagetables as per the platform memory map & initialize the MMU
603cf3183fSVarun Wadekar  ******************************************************************************/
613cf3183fSVarun Wadekar const mmap_region_t *plat_get_mmio_map(void)
623cf3183fSVarun Wadekar {
633cf3183fSVarun Wadekar 	/* MMIO space */
643cf3183fSVarun Wadekar 	return tegra_mmap;
653cf3183fSVarun Wadekar }
663cf3183fSVarun Wadekar 
673cf3183fSVarun Wadekar /*******************************************************************************
683cf3183fSVarun Wadekar  * Handler to get the System Counter Frequency
693cf3183fSVarun Wadekar  ******************************************************************************/
703cf3183fSVarun Wadekar unsigned int plat_get_syscnt_freq2(void)
713cf3183fSVarun Wadekar {
72*5d74d68eSVarun Wadekar 	return 31250000;
733cf3183fSVarun Wadekar }
743cf3183fSVarun Wadekar 
753cf3183fSVarun Wadekar /*******************************************************************************
763cf3183fSVarun Wadekar  * Maximum supported UART controllers
773cf3183fSVarun Wadekar  ******************************************************************************/
783cf3183fSVarun Wadekar #define TEGRA186_MAX_UART_PORTS		7
793cf3183fSVarun Wadekar 
803cf3183fSVarun Wadekar /*******************************************************************************
813cf3183fSVarun Wadekar  * This variable holds the UART port base addresses
823cf3183fSVarun Wadekar  ******************************************************************************/
833cf3183fSVarun Wadekar static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
843cf3183fSVarun Wadekar 	0,	/* undefined - treated as an error case */
853cf3183fSVarun Wadekar 	TEGRA_UARTA_BASE,
863cf3183fSVarun Wadekar 	TEGRA_UARTB_BASE,
873cf3183fSVarun Wadekar 	TEGRA_UARTC_BASE,
883cf3183fSVarun Wadekar 	TEGRA_UARTD_BASE,
893cf3183fSVarun Wadekar 	TEGRA_UARTE_BASE,
903cf3183fSVarun Wadekar 	TEGRA_UARTF_BASE,
913cf3183fSVarun Wadekar 	TEGRA_UARTG_BASE,
923cf3183fSVarun Wadekar };
933cf3183fSVarun Wadekar 
943cf3183fSVarun Wadekar /*******************************************************************************
953cf3183fSVarun Wadekar  * Retrieve the UART controller base to be used as the console
963cf3183fSVarun Wadekar  ******************************************************************************/
973cf3183fSVarun Wadekar uint32_t plat_get_console_from_id(int id)
983cf3183fSVarun Wadekar {
993cf3183fSVarun Wadekar 	if (id > TEGRA186_MAX_UART_PORTS)
1003cf3183fSVarun Wadekar 		return 0;
1013cf3183fSVarun Wadekar 
1023cf3183fSVarun Wadekar 	return tegra186_uart_addresses[id];
1033cf3183fSVarun Wadekar }
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