13cf3183fSVarun Wadekar /* 23cf3183fSVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 43cf3183fSVarun Wadekar * Redistribution and use in source and binary forms, with or without 53cf3183fSVarun Wadekar * modification, are permitted provided that the following conditions are met: 63cf3183fSVarun Wadekar * 73cf3183fSVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 83cf3183fSVarun Wadekar * list of conditions and the following disclaimer. 93cf3183fSVarun Wadekar * 103cf3183fSVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 113cf3183fSVarun Wadekar * this list of conditions and the following disclaimer in the documentation 123cf3183fSVarun Wadekar * and/or other materials provided with the distribution. 133cf3183fSVarun Wadekar * 143cf3183fSVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 153cf3183fSVarun Wadekar * to endorse or promote products derived from this software without specific 163cf3183fSVarun Wadekar * prior written permission. 173cf3183fSVarun Wadekar * 183cf3183fSVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 193cf3183fSVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 203cf3183fSVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 213cf3183fSVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 223cf3183fSVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 233cf3183fSVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 243cf3183fSVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 253cf3183fSVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 263cf3183fSVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 273cf3183fSVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 283cf3183fSVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 293cf3183fSVarun Wadekar */ 303cf3183fSVarun Wadekar 31*50cd8646SVarun Wadekar #include <arch_helpers.h> 32*50cd8646SVarun Wadekar #include <assert.h> 33*50cd8646SVarun Wadekar #include <bl_common.h> 343cf3183fSVarun Wadekar #include <console.h> 35*50cd8646SVarun Wadekar #include <context.h> 36*50cd8646SVarun Wadekar #include <context_mgmt.h> 37*50cd8646SVarun Wadekar #include <debug.h> 38*50cd8646SVarun Wadekar #include <denver.h> 39*50cd8646SVarun Wadekar #include <interrupt_mgmt.h> 40*50cd8646SVarun Wadekar #include <platform.h> 413cf3183fSVarun Wadekar #include <tegra_def.h> 42*50cd8646SVarun Wadekar #include <tegra_private.h> 433cf3183fSVarun Wadekar #include <xlat_tables.h> 443cf3183fSVarun Wadekar 45b67a7c7cSVarun Wadekar /******************************************************************************* 46b67a7c7cSVarun Wadekar * The Tegra power domain tree has a single system level power domain i.e. a 47b67a7c7cSVarun Wadekar * single root node. The first entry in the power domain descriptor specifies 48b67a7c7cSVarun Wadekar * the number of power domains at the highest power level. 49b67a7c7cSVarun Wadekar ******************************************************************************* 50b67a7c7cSVarun Wadekar */ 51b67a7c7cSVarun Wadekar const unsigned char tegra_power_domain_tree_desc[] = { 52b67a7c7cSVarun Wadekar /* No of root nodes */ 53b67a7c7cSVarun Wadekar 1, 54b67a7c7cSVarun Wadekar /* No of clusters */ 55b67a7c7cSVarun Wadekar PLATFORM_CLUSTER_COUNT, 56b67a7c7cSVarun Wadekar /* No of CPU cores - cluster0 */ 57b67a7c7cSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER, 58b67a7c7cSVarun Wadekar /* No of CPU cores - cluster1 */ 59b67a7c7cSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER 60b67a7c7cSVarun Wadekar }; 61b67a7c7cSVarun Wadekar 623cf3183fSVarun Wadekar /* 633cf3183fSVarun Wadekar * Table of regions to map using the MMU. 643cf3183fSVarun Wadekar */ 653cf3183fSVarun Wadekar static const mmap_region_t tegra_mmap[] = { 663cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 673cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 683cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 693cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 703cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 713cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 723cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB */ 733cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 743cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 753cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 7667bc721bSVarun Wadekar MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 7767bc721bSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 783cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 793cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 803cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 813cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 823cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x10000, /* 64KB */ 833cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 843cf3183fSVarun Wadekar {0} 853cf3183fSVarun Wadekar }; 863cf3183fSVarun Wadekar 873cf3183fSVarun Wadekar /******************************************************************************* 883cf3183fSVarun Wadekar * Set up the pagetables as per the platform memory map & initialize the MMU 893cf3183fSVarun Wadekar ******************************************************************************/ 903cf3183fSVarun Wadekar const mmap_region_t *plat_get_mmio_map(void) 913cf3183fSVarun Wadekar { 923cf3183fSVarun Wadekar /* MMIO space */ 933cf3183fSVarun Wadekar return tegra_mmap; 943cf3183fSVarun Wadekar } 953cf3183fSVarun Wadekar 963cf3183fSVarun Wadekar /******************************************************************************* 973cf3183fSVarun Wadekar * Handler to get the System Counter Frequency 983cf3183fSVarun Wadekar ******************************************************************************/ 993cf3183fSVarun Wadekar unsigned int plat_get_syscnt_freq2(void) 1003cf3183fSVarun Wadekar { 1015d74d68eSVarun Wadekar return 31250000; 1023cf3183fSVarun Wadekar } 1033cf3183fSVarun Wadekar 1043cf3183fSVarun Wadekar /******************************************************************************* 1053cf3183fSVarun Wadekar * Maximum supported UART controllers 1063cf3183fSVarun Wadekar ******************************************************************************/ 1073cf3183fSVarun Wadekar #define TEGRA186_MAX_UART_PORTS 7 1083cf3183fSVarun Wadekar 1093cf3183fSVarun Wadekar /******************************************************************************* 1103cf3183fSVarun Wadekar * This variable holds the UART port base addresses 1113cf3183fSVarun Wadekar ******************************************************************************/ 1123cf3183fSVarun Wadekar static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 1133cf3183fSVarun Wadekar 0, /* undefined - treated as an error case */ 1143cf3183fSVarun Wadekar TEGRA_UARTA_BASE, 1153cf3183fSVarun Wadekar TEGRA_UARTB_BASE, 1163cf3183fSVarun Wadekar TEGRA_UARTC_BASE, 1173cf3183fSVarun Wadekar TEGRA_UARTD_BASE, 1183cf3183fSVarun Wadekar TEGRA_UARTE_BASE, 1193cf3183fSVarun Wadekar TEGRA_UARTF_BASE, 1203cf3183fSVarun Wadekar TEGRA_UARTG_BASE, 1213cf3183fSVarun Wadekar }; 1223cf3183fSVarun Wadekar 1233cf3183fSVarun Wadekar /******************************************************************************* 1243cf3183fSVarun Wadekar * Retrieve the UART controller base to be used as the console 1253cf3183fSVarun Wadekar ******************************************************************************/ 1263cf3183fSVarun Wadekar uint32_t plat_get_console_from_id(int id) 1273cf3183fSVarun Wadekar { 1283cf3183fSVarun Wadekar if (id > TEGRA186_MAX_UART_PORTS) 1293cf3183fSVarun Wadekar return 0; 1303cf3183fSVarun Wadekar 1313cf3183fSVarun Wadekar return tegra186_uart_addresses[id]; 1323cf3183fSVarun Wadekar } 133*50cd8646SVarun Wadekar 134*50cd8646SVarun Wadekar /* Secure IRQs for Tegra186 */ 135*50cd8646SVarun Wadekar static const irq_sec_cfg_t tegra186_sec_irqs[] = { 136*50cd8646SVarun Wadekar { 137*50cd8646SVarun Wadekar TEGRA186_TOP_WDT_IRQ, 138*50cd8646SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 139*50cd8646SVarun Wadekar INTR_TYPE_EL3, 140*50cd8646SVarun Wadekar }, 141*50cd8646SVarun Wadekar { 142*50cd8646SVarun Wadekar TEGRA186_AON_WDT_IRQ, 143*50cd8646SVarun Wadekar TEGRA186_SEC_IRQ_TARGET_MASK, 144*50cd8646SVarun Wadekar INTR_TYPE_EL3, 145*50cd8646SVarun Wadekar }, 146*50cd8646SVarun Wadekar }; 147*50cd8646SVarun Wadekar 148*50cd8646SVarun Wadekar /******************************************************************************* 149*50cd8646SVarun Wadekar * Initialize the GIC and SGIs 150*50cd8646SVarun Wadekar ******************************************************************************/ 151*50cd8646SVarun Wadekar void plat_gic_setup(void) 152*50cd8646SVarun Wadekar { 153*50cd8646SVarun Wadekar tegra_gic_setup(tegra186_sec_irqs, 154*50cd8646SVarun Wadekar sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); 155*50cd8646SVarun Wadekar 156*50cd8646SVarun Wadekar /* 157*50cd8646SVarun Wadekar * Initialize the FIQ handler only if the platform supports any 158*50cd8646SVarun Wadekar * FIQ interrupt sources. 159*50cd8646SVarun Wadekar */ 160*50cd8646SVarun Wadekar if (sizeof(tegra186_sec_irqs) > 0) 161*50cd8646SVarun Wadekar tegra_fiq_handler_setup(); 162*50cd8646SVarun Wadekar } 163