1*3cf3183fSVarun Wadekar /* 2*3cf3183fSVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*3cf3183fSVarun Wadekar * 4*3cf3183fSVarun Wadekar * Redistribution and use in source and binary forms, with or without 5*3cf3183fSVarun Wadekar * modification, are permitted provided that the following conditions are met: 6*3cf3183fSVarun Wadekar * 7*3cf3183fSVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8*3cf3183fSVarun Wadekar * list of conditions and the following disclaimer. 9*3cf3183fSVarun Wadekar * 10*3cf3183fSVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11*3cf3183fSVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12*3cf3183fSVarun Wadekar * and/or other materials provided with the distribution. 13*3cf3183fSVarun Wadekar * 14*3cf3183fSVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15*3cf3183fSVarun Wadekar * to endorse or promote products derived from this software without specific 16*3cf3183fSVarun Wadekar * prior written permission. 17*3cf3183fSVarun Wadekar * 18*3cf3183fSVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*3cf3183fSVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*3cf3183fSVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*3cf3183fSVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*3cf3183fSVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*3cf3183fSVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*3cf3183fSVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*3cf3183fSVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*3cf3183fSVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*3cf3183fSVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*3cf3183fSVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29*3cf3183fSVarun Wadekar */ 30*3cf3183fSVarun Wadekar 31*3cf3183fSVarun Wadekar #include <console.h> 32*3cf3183fSVarun Wadekar #include <tegra_def.h> 33*3cf3183fSVarun Wadekar #include <xlat_tables.h> 34*3cf3183fSVarun Wadekar 35*3cf3183fSVarun Wadekar /* 36*3cf3183fSVarun Wadekar * Table of regions to map using the MMU. 37*3cf3183fSVarun Wadekar */ 38*3cf3183fSVarun Wadekar static const mmap_region_t tegra_mmap[] = { 39*3cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 40*3cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 41*3cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 42*3cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 43*3cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 44*3cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 45*3cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB */ 46*3cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 47*3cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 48*3cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 49*3cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 50*3cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 51*3cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 52*3cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 53*3cf3183fSVarun Wadekar MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x10000, /* 64KB */ 54*3cf3183fSVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 55*3cf3183fSVarun Wadekar {0} 56*3cf3183fSVarun Wadekar }; 57*3cf3183fSVarun Wadekar 58*3cf3183fSVarun Wadekar /******************************************************************************* 59*3cf3183fSVarun Wadekar * Set up the pagetables as per the platform memory map & initialize the MMU 60*3cf3183fSVarun Wadekar ******************************************************************************/ 61*3cf3183fSVarun Wadekar const mmap_region_t *plat_get_mmio_map(void) 62*3cf3183fSVarun Wadekar { 63*3cf3183fSVarun Wadekar /* MMIO space */ 64*3cf3183fSVarun Wadekar return tegra_mmap; 65*3cf3183fSVarun Wadekar } 66*3cf3183fSVarun Wadekar 67*3cf3183fSVarun Wadekar /******************************************************************************* 68*3cf3183fSVarun Wadekar * Handler to get the System Counter Frequency 69*3cf3183fSVarun Wadekar ******************************************************************************/ 70*3cf3183fSVarun Wadekar unsigned int plat_get_syscnt_freq2(void) 71*3cf3183fSVarun Wadekar { 72*3cf3183fSVarun Wadekar return 38400000; 73*3cf3183fSVarun Wadekar } 74*3cf3183fSVarun Wadekar 75*3cf3183fSVarun Wadekar /******************************************************************************* 76*3cf3183fSVarun Wadekar * Maximum supported UART controllers 77*3cf3183fSVarun Wadekar ******************************************************************************/ 78*3cf3183fSVarun Wadekar #define TEGRA186_MAX_UART_PORTS 7 79*3cf3183fSVarun Wadekar 80*3cf3183fSVarun Wadekar /******************************************************************************* 81*3cf3183fSVarun Wadekar * This variable holds the UART port base addresses 82*3cf3183fSVarun Wadekar ******************************************************************************/ 83*3cf3183fSVarun Wadekar static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 84*3cf3183fSVarun Wadekar 0, /* undefined - treated as an error case */ 85*3cf3183fSVarun Wadekar TEGRA_UARTA_BASE, 86*3cf3183fSVarun Wadekar TEGRA_UARTB_BASE, 87*3cf3183fSVarun Wadekar TEGRA_UARTC_BASE, 88*3cf3183fSVarun Wadekar TEGRA_UARTD_BASE, 89*3cf3183fSVarun Wadekar TEGRA_UARTE_BASE, 90*3cf3183fSVarun Wadekar TEGRA_UARTF_BASE, 91*3cf3183fSVarun Wadekar TEGRA_UARTG_BASE, 92*3cf3183fSVarun Wadekar }; 93*3cf3183fSVarun Wadekar 94*3cf3183fSVarun Wadekar /******************************************************************************* 95*3cf3183fSVarun Wadekar * Retrieve the UART controller base to be used as the console 96*3cf3183fSVarun Wadekar ******************************************************************************/ 97*3cf3183fSVarun Wadekar uint32_t plat_get_console_from_id(int id) 98*3cf3183fSVarun Wadekar { 99*3cf3183fSVarun Wadekar if (id > TEGRA186_MAX_UART_PORTS) 100*3cf3183fSVarun Wadekar return 0; 101*3cf3183fSVarun Wadekar 102*3cf3183fSVarun Wadekar return tegra186_uart_addresses[id]; 103*3cf3183fSVarun Wadekar } 104