1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <arch_helpers.h> 10 #include <common/debug.h> 11 #include <lib/mmio.h> 12 13 #include <mce.h> 14 #include <tegra_def.h> 15 #include <tegra_private.h> 16 17 #define MISCREG_AA64_RST_LOW 0x2004U 18 #define MISCREG_AA64_RST_HIGH 0x2008U 19 20 #define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658U 21 #define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65CU 22 23 #define CPU_RESET_MODE_AA64 1U 24 25 extern void memcpy16(void *dest, const void *src, unsigned int length); 26 27 extern uint64_t tegra_bl31_phys_base; 28 extern uint64_t __tegra186_cpu_reset_handler_end; 29 30 /******************************************************************************* 31 * Setup secondary CPU vectors 32 ******************************************************************************/ 33 void plat_secondary_setup(void) 34 { 35 uint32_t addr_low, addr_high; 36 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 37 uint64_t cpu_reset_handler_base; 38 39 INFO("Setting up secondary CPU boot\n"); 40 41 if ((tegra_bl31_phys_base >= TEGRA_TZRAM_BASE) && 42 (tegra_bl31_phys_base <= (TEGRA_TZRAM_BASE + TEGRA_TZRAM_SIZE))) { 43 44 /* 45 * The BL31 code resides in the TZSRAM which loses state 46 * when we enter System Suspend. Copy the wakeup trampoline 47 * code to TZDRAM to help us exit from System Suspend. 48 */ 49 cpu_reset_handler_base = params_from_bl2->tzdram_base; 50 memcpy16((void *)((uintptr_t)cpu_reset_handler_base), 51 (void *)(uintptr_t)tegra186_cpu_reset_handler, 52 (uintptr_t)&__tegra186_cpu_reset_handler_end - 53 (uintptr_t)tegra186_cpu_reset_handler); 54 55 } else { 56 cpu_reset_handler_base = (uintptr_t)tegra_secure_entrypoint; 57 } 58 59 addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64; 60 addr_high = (uint32_t)((cpu_reset_handler_base >> 32U) & 0x7ffU); 61 62 /* write lower 32 bits first, then the upper 11 bits */ 63 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); 64 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); 65 66 /* save reset vector to be used during SYSTEM_SUSPEND exit */ 67 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_0, 68 addr_low); 69 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_1, 70 addr_high); 71 72 /* update reset vector address to the CCPLEX */ 73 (void)mce_update_reset_vector(); 74 } 75