1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <arch_helpers.h> 10 #include <common/debug.h> 11 #include <lib/mmio.h> 12 13 #include <mce.h> 14 #include <tegra186_private.h> 15 #include <tegra_def.h> 16 #include <tegra_private.h> 17 18 #define MISCREG_AA64_RST_LOW 0x2004U 19 #define MISCREG_AA64_RST_HIGH 0x2008U 20 21 #define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658U 22 #define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65CU 23 24 #define CPU_RESET_MODE_AA64 1U 25 26 extern void memcpy16(void *dest, const void *src, unsigned int length); 27 28 /******************************************************************************* 29 * Setup secondary CPU vectors 30 ******************************************************************************/ 31 void plat_secondary_setup(void) 32 { 33 uint32_t addr_low, addr_high; 34 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 35 uint64_t cpu_reset_handler_base, cpu_reset_handler_size; 36 37 INFO("Setting up secondary CPU boot\n"); 38 39 /* 40 * The BL31 code resides in the TZSRAM which loses state 41 * when we enter System Suspend. Copy the wakeup trampoline 42 * code to TZDRAM to help us exit from System Suspend. 43 */ 44 cpu_reset_handler_base = tegra186_get_cpu_reset_handler_base(); 45 cpu_reset_handler_size = tegra186_get_cpu_reset_handler_size(); 46 (void)memcpy16((void *)(uintptr_t)params_from_bl2->tzdram_base, 47 (const void *)(uintptr_t)cpu_reset_handler_base, 48 cpu_reset_handler_size); 49 50 /* TZDRAM base will be used as the "resume" address */ 51 addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64; 52 addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU); 53 54 /* write lower 32 bits first, then the upper 11 bits */ 55 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); 56 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); 57 58 /* save reset vector to be used during SYSTEM_SUSPEND exit */ 59 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO, 60 addr_low); 61 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI, 62 addr_high); 63 64 /* update reset vector address to the CCPLEX */ 65 (void)mce_update_reset_vector(); 66 } 67