1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <debug.h> 32 #include <mce.h> 33 #include <mmio.h> 34 #include <tegra_def.h> 35 36 #define MISCREG_CPU_RESET_VECTOR 0x2000 37 #define MISCREG_AA64_RST_LOW 0x2004 38 #define MISCREG_AA64_RST_HIGH 0x2008 39 40 #define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658 41 #define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65C 42 43 #define CPU_RESET_MODE_AA64 1 44 45 extern void tegra_secure_entrypoint(void); 46 47 /******************************************************************************* 48 * Setup secondary CPU vectors 49 ******************************************************************************/ 50 void plat_secondary_setup(void) 51 { 52 uint32_t addr_low, addr_high; 53 uint64_t reset_addr = (uint64_t)tegra_secure_entrypoint; 54 55 INFO("Setting up secondary CPU boot\n"); 56 57 addr_low = (uint32_t)reset_addr | CPU_RESET_MODE_AA64; 58 addr_high = (uint32_t)((reset_addr >> 32) & 0x7ff); 59 60 /* write lower 32 bits first, then the upper 11 bits */ 61 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); 62 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); 63 64 /* save reset vector to be used during SYSTEM_SUSPEND exit */ 65 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_0, 66 addr_low); 67 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_1, 68 addr_high); 69 70 /* update reset vector address to the CCPLEX */ 71 mce_update_reset_vector(addr_low, addr_high); 72 } 73