13cf3183fSVarun Wadekar /* 23cf3183fSVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 43cf3183fSVarun Wadekar * Redistribution and use in source and binary forms, with or without 53cf3183fSVarun Wadekar * modification, are permitted provided that the following conditions are met: 63cf3183fSVarun Wadekar * 73cf3183fSVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 83cf3183fSVarun Wadekar * list of conditions and the following disclaimer. 93cf3183fSVarun Wadekar * 103cf3183fSVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 113cf3183fSVarun Wadekar * this list of conditions and the following disclaimer in the documentation 123cf3183fSVarun Wadekar * and/or other materials provided with the distribution. 133cf3183fSVarun Wadekar * 143cf3183fSVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 153cf3183fSVarun Wadekar * to endorse or promote products derived from this software without specific 163cf3183fSVarun Wadekar * prior written permission. 173cf3183fSVarun Wadekar * 183cf3183fSVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 193cf3183fSVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 203cf3183fSVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 213cf3183fSVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 223cf3183fSVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 233cf3183fSVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 243cf3183fSVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 253cf3183fSVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 263cf3183fSVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 273cf3183fSVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 283cf3183fSVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 293cf3183fSVarun Wadekar */ 303cf3183fSVarun Wadekar 31*b47d97b3SVarun Wadekar #include <debug.h> 32*b47d97b3SVarun Wadekar #include <mce.h> 33*b47d97b3SVarun Wadekar #include <mmio.h> 34*b47d97b3SVarun Wadekar #include <tegra_def.h> 35*b47d97b3SVarun Wadekar 36*b47d97b3SVarun Wadekar #define MISCREG_CPU_RESET_VECTOR 0x2000 37*b47d97b3SVarun Wadekar #define MISCREG_AA64_RST_LOW 0x2004 38*b47d97b3SVarun Wadekar #define MISCREG_AA64_RST_HIGH 0x2008 39*b47d97b3SVarun Wadekar 40*b47d97b3SVarun Wadekar #define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658 41*b47d97b3SVarun Wadekar #define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65C 42*b47d97b3SVarun Wadekar 43*b47d97b3SVarun Wadekar #define CPU_RESET_MODE_AA64 1 44*b47d97b3SVarun Wadekar 45*b47d97b3SVarun Wadekar extern void tegra_secure_entrypoint(void); 46*b47d97b3SVarun Wadekar 473cf3183fSVarun Wadekar /******************************************************************************* 483cf3183fSVarun Wadekar * Setup secondary CPU vectors 493cf3183fSVarun Wadekar ******************************************************************************/ 503cf3183fSVarun Wadekar void plat_secondary_setup(void) 513cf3183fSVarun Wadekar { 52*b47d97b3SVarun Wadekar uint32_t addr_low, addr_high; 53*b47d97b3SVarun Wadekar uint64_t reset_addr = (uint64_t)tegra_secure_entrypoint; 54*b47d97b3SVarun Wadekar 55*b47d97b3SVarun Wadekar INFO("Setting up secondary CPU boot\n"); 56*b47d97b3SVarun Wadekar 57*b47d97b3SVarun Wadekar addr_low = (uint32_t)reset_addr | CPU_RESET_MODE_AA64; 58*b47d97b3SVarun Wadekar addr_high = (uint32_t)((reset_addr >> 32) & 0x7ff); 59*b47d97b3SVarun Wadekar 60*b47d97b3SVarun Wadekar /* write lower 32 bits first, then the upper 11 bits */ 61*b47d97b3SVarun Wadekar mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); 62*b47d97b3SVarun Wadekar mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); 63*b47d97b3SVarun Wadekar 64*b47d97b3SVarun Wadekar /* save reset vector to be used during SYSTEM_SUSPEND exit */ 65*b47d97b3SVarun Wadekar mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_0, 66*b47d97b3SVarun Wadekar addr_low); 67*b47d97b3SVarun Wadekar mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_1, 68*b47d97b3SVarun Wadekar addr_high); 69*b47d97b3SVarun Wadekar 70*b47d97b3SVarun Wadekar /* update reset vector address to the CCPLEX */ 71*b47d97b3SVarun Wadekar mce_update_reset_vector(addr_low, addr_high); 723cf3183fSVarun Wadekar } 73