13cf3183fSVarun Wadekar /* 293c78ed2SAntonio Nino Diaz * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*8336c94dSVarun Wadekar * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 43cf3183fSVarun Wadekar * 582cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 63cf3183fSVarun Wadekar */ 73cf3183fSVarun Wadekar 868c7de6fSVarun Wadekar #include <string.h> 909d40e0eSAntonio Nino Diaz 1009d40e0eSAntonio Nino Diaz #include <arch_helpers.h> 1109d40e0eSAntonio Nino Diaz #include <common/debug.h> 1209d40e0eSAntonio Nino Diaz #include <lib/mmio.h> 1309d40e0eSAntonio Nino Diaz 1409d40e0eSAntonio Nino Diaz #include <mce.h> 157191566cSVarun Wadekar #include <tegra186_private.h> 16b47d97b3SVarun Wadekar #include <tegra_def.h> 1768c7de6fSVarun Wadekar #include <tegra_private.h> 18b47d97b3SVarun Wadekar 19592035d0SAnthony Zhou #define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658U 20592035d0SAnthony Zhou #define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65CU 21b47d97b3SVarun Wadekar 22592035d0SAnthony Zhou #define CPU_RESET_MODE_AA64 1U 23b47d97b3SVarun Wadekar 2493c78ed2SAntonio Nino Diaz extern void memcpy16(void *dest, const void *src, unsigned int length); 2593c78ed2SAntonio Nino Diaz 263cf3183fSVarun Wadekar /******************************************************************************* 273cf3183fSVarun Wadekar * Setup secondary CPU vectors 283cf3183fSVarun Wadekar ******************************************************************************/ 293cf3183fSVarun Wadekar void plat_secondary_setup(void) 303cf3183fSVarun Wadekar { 31b47d97b3SVarun Wadekar uint32_t addr_low, addr_high; 32592035d0SAnthony Zhou const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 337191566cSVarun Wadekar uint64_t cpu_reset_handler_base, cpu_reset_handler_size; 34b47d97b3SVarun Wadekar 35b47d97b3SVarun Wadekar INFO("Setting up secondary CPU boot\n"); 36b47d97b3SVarun Wadekar 3768c7de6fSVarun Wadekar /* 3868c7de6fSVarun Wadekar * The BL31 code resides in the TZSRAM which loses state 3968c7de6fSVarun Wadekar * when we enter System Suspend. Copy the wakeup trampoline 4068c7de6fSVarun Wadekar * code to TZDRAM to help us exit from System Suspend. 4168c7de6fSVarun Wadekar */ 427191566cSVarun Wadekar cpu_reset_handler_base = tegra186_get_cpu_reset_handler_base(); 437191566cSVarun Wadekar cpu_reset_handler_size = tegra186_get_cpu_reset_handler_size(); 447191566cSVarun Wadekar (void)memcpy16((void *)(uintptr_t)params_from_bl2->tzdram_base, 457191566cSVarun Wadekar (const void *)(uintptr_t)cpu_reset_handler_base, 467191566cSVarun Wadekar cpu_reset_handler_size); 4768c7de6fSVarun Wadekar 487191566cSVarun Wadekar /* TZDRAM base will be used as the "resume" address */ 497191566cSVarun Wadekar addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64; 507191566cSVarun Wadekar addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU); 51b47d97b3SVarun Wadekar 52b47d97b3SVarun Wadekar /* save reset vector to be used during SYSTEM_SUSPEND exit */ 53601a8e54SSteven Kao mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO, 54b47d97b3SVarun Wadekar addr_low); 55601a8e54SSteven Kao mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI, 56b47d97b3SVarun Wadekar addr_high); 573cf3183fSVarun Wadekar } 58