13cf3183fSVarun Wadekar /* 23cf3183fSVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 53cf3183fSVarun Wadekar */ 63cf3183fSVarun Wadekar 768c7de6fSVarun Wadekar #include <arch_helpers.h> 8b47d97b3SVarun Wadekar #include <debug.h> 9b47d97b3SVarun Wadekar #include <mce.h> 10b47d97b3SVarun Wadekar #include <mmio.h> 1168c7de6fSVarun Wadekar #include <string.h> 12b47d97b3SVarun Wadekar #include <tegra_def.h> 1368c7de6fSVarun Wadekar #include <tegra_private.h> 14b47d97b3SVarun Wadekar 15b47d97b3SVarun Wadekar #define MISCREG_CPU_RESET_VECTOR 0x2000 16b47d97b3SVarun Wadekar #define MISCREG_AA64_RST_LOW 0x2004 17b47d97b3SVarun Wadekar #define MISCREG_AA64_RST_HIGH 0x2008 18b47d97b3SVarun Wadekar 19b47d97b3SVarun Wadekar #define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658 20b47d97b3SVarun Wadekar #define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65C 21b47d97b3SVarun Wadekar 22b47d97b3SVarun Wadekar #define CPU_RESET_MODE_AA64 1 23b47d97b3SVarun Wadekar 2468c7de6fSVarun Wadekar extern uint64_t tegra_bl31_phys_base; 2568c7de6fSVarun Wadekar extern uint64_t __tegra186_cpu_reset_handler_end; 26b47d97b3SVarun Wadekar 273cf3183fSVarun Wadekar /******************************************************************************* 283cf3183fSVarun Wadekar * Setup secondary CPU vectors 293cf3183fSVarun Wadekar ******************************************************************************/ 303cf3183fSVarun Wadekar void plat_secondary_setup(void) 313cf3183fSVarun Wadekar { 32b47d97b3SVarun Wadekar uint32_t addr_low, addr_high; 3368c7de6fSVarun Wadekar plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 3468c7de6fSVarun Wadekar uint64_t cpu_reset_handler_base; 35b47d97b3SVarun Wadekar 36b47d97b3SVarun Wadekar INFO("Setting up secondary CPU boot\n"); 37b47d97b3SVarun Wadekar 3868c7de6fSVarun Wadekar if ((tegra_bl31_phys_base >= TEGRA_TZRAM_BASE) && 3968c7de6fSVarun Wadekar (tegra_bl31_phys_base <= (TEGRA_TZRAM_BASE + TEGRA_TZRAM_SIZE))) { 4068c7de6fSVarun Wadekar 4168c7de6fSVarun Wadekar /* 4268c7de6fSVarun Wadekar * The BL31 code resides in the TZSRAM which loses state 4368c7de6fSVarun Wadekar * when we enter System Suspend. Copy the wakeup trampoline 4468c7de6fSVarun Wadekar * code to TZDRAM to help us exit from System Suspend. 4568c7de6fSVarun Wadekar */ 4668c7de6fSVarun Wadekar cpu_reset_handler_base = params_from_bl2->tzdram_base; 4768c7de6fSVarun Wadekar memcpy16((void *)((uintptr_t)cpu_reset_handler_base), 4868c7de6fSVarun Wadekar (void *)(uintptr_t)tegra186_cpu_reset_handler, 4968c7de6fSVarun Wadekar (uintptr_t)&__tegra186_cpu_reset_handler_end - 5068c7de6fSVarun Wadekar (uintptr_t)tegra186_cpu_reset_handler); 5168c7de6fSVarun Wadekar 5268c7de6fSVarun Wadekar } else { 5368c7de6fSVarun Wadekar cpu_reset_handler_base = (uintptr_t)tegra_secure_entrypoint; 5468c7de6fSVarun Wadekar } 5568c7de6fSVarun Wadekar 5668c7de6fSVarun Wadekar addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64; 5768c7de6fSVarun Wadekar addr_high = (uint32_t)((cpu_reset_handler_base >> 32) & 0x7ff); 58b47d97b3SVarun Wadekar 59b47d97b3SVarun Wadekar /* write lower 32 bits first, then the upper 11 bits */ 60b47d97b3SVarun Wadekar mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); 61b47d97b3SVarun Wadekar mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); 62b47d97b3SVarun Wadekar 63b47d97b3SVarun Wadekar /* save reset vector to be used during SYSTEM_SUSPEND exit */ 64b47d97b3SVarun Wadekar mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_0, 65b47d97b3SVarun Wadekar addr_low); 66b47d97b3SVarun Wadekar mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_1, 67b47d97b3SVarun Wadekar addr_high); 68b47d97b3SVarun Wadekar 69b47d97b3SVarun Wadekar /* update reset vector address to the CCPLEX */ 70a259293eSKrishna Sitaraman mce_update_reset_vector(); 713cf3183fSVarun Wadekar } 72