13cf3183fSVarun Wadekar /* 23cf3183fSVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 43cf3183fSVarun Wadekar * Redistribution and use in source and binary forms, with or without 53cf3183fSVarun Wadekar * modification, are permitted provided that the following conditions are met: 63cf3183fSVarun Wadekar * 73cf3183fSVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 83cf3183fSVarun Wadekar * list of conditions and the following disclaimer. 93cf3183fSVarun Wadekar * 103cf3183fSVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 113cf3183fSVarun Wadekar * this list of conditions and the following disclaimer in the documentation 123cf3183fSVarun Wadekar * and/or other materials provided with the distribution. 133cf3183fSVarun Wadekar * 143cf3183fSVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 153cf3183fSVarun Wadekar * to endorse or promote products derived from this software without specific 163cf3183fSVarun Wadekar * prior written permission. 173cf3183fSVarun Wadekar * 183cf3183fSVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 193cf3183fSVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 203cf3183fSVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 213cf3183fSVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 223cf3183fSVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 233cf3183fSVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 243cf3183fSVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 253cf3183fSVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 263cf3183fSVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 273cf3183fSVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 283cf3183fSVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 293cf3183fSVarun Wadekar */ 303cf3183fSVarun Wadekar 31*68c7de6fSVarun Wadekar #include <arch_helpers.h> 32b47d97b3SVarun Wadekar #include <debug.h> 33b47d97b3SVarun Wadekar #include <mce.h> 34b47d97b3SVarun Wadekar #include <mmio.h> 35*68c7de6fSVarun Wadekar #include <string.h> 36b47d97b3SVarun Wadekar #include <tegra_def.h> 37*68c7de6fSVarun Wadekar #include <tegra_private.h> 38b47d97b3SVarun Wadekar 39b47d97b3SVarun Wadekar #define MISCREG_CPU_RESET_VECTOR 0x2000 40b47d97b3SVarun Wadekar #define MISCREG_AA64_RST_LOW 0x2004 41b47d97b3SVarun Wadekar #define MISCREG_AA64_RST_HIGH 0x2008 42b47d97b3SVarun Wadekar 43b47d97b3SVarun Wadekar #define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658 44b47d97b3SVarun Wadekar #define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65C 45b47d97b3SVarun Wadekar 46b47d97b3SVarun Wadekar #define CPU_RESET_MODE_AA64 1 47b47d97b3SVarun Wadekar 48*68c7de6fSVarun Wadekar extern uint64_t tegra_bl31_phys_base; 49*68c7de6fSVarun Wadekar extern uint64_t __tegra186_cpu_reset_handler_end; 50b47d97b3SVarun Wadekar 513cf3183fSVarun Wadekar /******************************************************************************* 523cf3183fSVarun Wadekar * Setup secondary CPU vectors 533cf3183fSVarun Wadekar ******************************************************************************/ 543cf3183fSVarun Wadekar void plat_secondary_setup(void) 553cf3183fSVarun Wadekar { 56b47d97b3SVarun Wadekar uint32_t addr_low, addr_high; 57*68c7de6fSVarun Wadekar plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 58*68c7de6fSVarun Wadekar uint64_t cpu_reset_handler_base; 59b47d97b3SVarun Wadekar 60b47d97b3SVarun Wadekar INFO("Setting up secondary CPU boot\n"); 61b47d97b3SVarun Wadekar 62*68c7de6fSVarun Wadekar if ((tegra_bl31_phys_base >= TEGRA_TZRAM_BASE) && 63*68c7de6fSVarun Wadekar (tegra_bl31_phys_base <= (TEGRA_TZRAM_BASE + TEGRA_TZRAM_SIZE))) { 64*68c7de6fSVarun Wadekar 65*68c7de6fSVarun Wadekar /* 66*68c7de6fSVarun Wadekar * The BL31 code resides in the TZSRAM which loses state 67*68c7de6fSVarun Wadekar * when we enter System Suspend. Copy the wakeup trampoline 68*68c7de6fSVarun Wadekar * code to TZDRAM to help us exit from System Suspend. 69*68c7de6fSVarun Wadekar */ 70*68c7de6fSVarun Wadekar cpu_reset_handler_base = params_from_bl2->tzdram_base; 71*68c7de6fSVarun Wadekar memcpy16((void *)((uintptr_t)cpu_reset_handler_base), 72*68c7de6fSVarun Wadekar (void *)(uintptr_t)tegra186_cpu_reset_handler, 73*68c7de6fSVarun Wadekar (uintptr_t)&__tegra186_cpu_reset_handler_end - 74*68c7de6fSVarun Wadekar (uintptr_t)tegra186_cpu_reset_handler); 75*68c7de6fSVarun Wadekar 76*68c7de6fSVarun Wadekar } else { 77*68c7de6fSVarun Wadekar cpu_reset_handler_base = (uintptr_t)tegra_secure_entrypoint; 78*68c7de6fSVarun Wadekar } 79*68c7de6fSVarun Wadekar 80*68c7de6fSVarun Wadekar addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64; 81*68c7de6fSVarun Wadekar addr_high = (uint32_t)((cpu_reset_handler_base >> 32) & 0x7ff); 82b47d97b3SVarun Wadekar 83b47d97b3SVarun Wadekar /* write lower 32 bits first, then the upper 11 bits */ 84b47d97b3SVarun Wadekar mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); 85b47d97b3SVarun Wadekar mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); 86b47d97b3SVarun Wadekar 87b47d97b3SVarun Wadekar /* save reset vector to be used during SYSTEM_SUSPEND exit */ 88b47d97b3SVarun Wadekar mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_0, 89b47d97b3SVarun Wadekar addr_low); 90b47d97b3SVarun Wadekar mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_1, 91b47d97b3SVarun Wadekar addr_high); 92b47d97b3SVarun Wadekar 93b47d97b3SVarun Wadekar /* update reset vector address to the CCPLEX */ 94b47d97b3SVarun Wadekar mce_update_reset_vector(addr_low, addr_high); 953cf3183fSVarun Wadekar } 96