13cf3183fSVarun Wadekar /* 293c78ed2SAntonio Nino Diaz * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 53cf3183fSVarun Wadekar */ 63cf3183fSVarun Wadekar 768c7de6fSVarun Wadekar #include <string.h> 809d40e0eSAntonio Nino Diaz 909d40e0eSAntonio Nino Diaz #include <arch_helpers.h> 1009d40e0eSAntonio Nino Diaz #include <common/debug.h> 1109d40e0eSAntonio Nino Diaz #include <lib/mmio.h> 1209d40e0eSAntonio Nino Diaz 1309d40e0eSAntonio Nino Diaz #include <mce.h> 147191566cSVarun Wadekar #include <tegra186_private.h> 15b47d97b3SVarun Wadekar #include <tegra_def.h> 1668c7de6fSVarun Wadekar #include <tegra_private.h> 17b47d97b3SVarun Wadekar 18592035d0SAnthony Zhou #define MISCREG_AA64_RST_LOW 0x2004U 19592035d0SAnthony Zhou #define MISCREG_AA64_RST_HIGH 0x2008U 20b47d97b3SVarun Wadekar 21592035d0SAnthony Zhou #define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658U 22592035d0SAnthony Zhou #define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65CU 23b47d97b3SVarun Wadekar 24592035d0SAnthony Zhou #define CPU_RESET_MODE_AA64 1U 25b47d97b3SVarun Wadekar 2693c78ed2SAntonio Nino Diaz extern void memcpy16(void *dest, const void *src, unsigned int length); 2793c78ed2SAntonio Nino Diaz 283cf3183fSVarun Wadekar /******************************************************************************* 293cf3183fSVarun Wadekar * Setup secondary CPU vectors 303cf3183fSVarun Wadekar ******************************************************************************/ 313cf3183fSVarun Wadekar void plat_secondary_setup(void) 323cf3183fSVarun Wadekar { 33b47d97b3SVarun Wadekar uint32_t addr_low, addr_high; 34592035d0SAnthony Zhou const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 357191566cSVarun Wadekar uint64_t cpu_reset_handler_base, cpu_reset_handler_size; 36b47d97b3SVarun Wadekar 37b47d97b3SVarun Wadekar INFO("Setting up secondary CPU boot\n"); 38b47d97b3SVarun Wadekar 3968c7de6fSVarun Wadekar /* 4068c7de6fSVarun Wadekar * The BL31 code resides in the TZSRAM which loses state 4168c7de6fSVarun Wadekar * when we enter System Suspend. Copy the wakeup trampoline 4268c7de6fSVarun Wadekar * code to TZDRAM to help us exit from System Suspend. 4368c7de6fSVarun Wadekar */ 447191566cSVarun Wadekar cpu_reset_handler_base = tegra186_get_cpu_reset_handler_base(); 457191566cSVarun Wadekar cpu_reset_handler_size = tegra186_get_cpu_reset_handler_size(); 467191566cSVarun Wadekar (void)memcpy16((void *)(uintptr_t)params_from_bl2->tzdram_base, 477191566cSVarun Wadekar (const void *)(uintptr_t)cpu_reset_handler_base, 487191566cSVarun Wadekar cpu_reset_handler_size); 4968c7de6fSVarun Wadekar 507191566cSVarun Wadekar /* TZDRAM base will be used as the "resume" address */ 517191566cSVarun Wadekar addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64; 527191566cSVarun Wadekar addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU); 53b47d97b3SVarun Wadekar 54b47d97b3SVarun Wadekar /* write lower 32 bits first, then the upper 11 bits */ 55b47d97b3SVarun Wadekar mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); 56b47d97b3SVarun Wadekar mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); 57b47d97b3SVarun Wadekar 58b47d97b3SVarun Wadekar /* save reset vector to be used during SYSTEM_SUSPEND exit */ 59*601a8e54SSteven Kao mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO, 60b47d97b3SVarun Wadekar addr_low); 61*601a8e54SSteven Kao mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI, 62b47d97b3SVarun Wadekar addr_high); 63b47d97b3SVarun Wadekar 64b47d97b3SVarun Wadekar /* update reset vector address to the CCPLEX */ 65592035d0SAnthony Zhou (void)mce_update_reset_vector(); 663cf3183fSVarun Wadekar } 67