1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl_common.h> 35 #include <context.h> 36 #include <context_mgmt.h> 37 #include <debug.h> 38 #include <denver.h> 39 #include <mce.h> 40 #include <psci.h> 41 #include <smmu.h> 42 #include <string.h> 43 #include <t18x_ari.h> 44 #include <tegra_private.h> 45 46 extern void prepare_cpu_pwr_dwn(void); 47 extern void tegra186_cpu_reset_handler(void); 48 extern uint32_t __tegra186_cpu_reset_handler_data, 49 __tegra186_cpu_reset_handler_end; 50 51 /* TZDRAM offset for saving SMMU context */ 52 #define TEGRA186_SMMU_CTX_OFFSET 16 53 54 /* state id mask */ 55 #define TEGRA186_STATE_ID_MASK 0xF 56 /* constants to get power state's wake time */ 57 #define TEGRA186_WAKE_TIME_MASK 0xFFFFFF 58 #define TEGRA186_WAKE_TIME_SHIFT 4 59 /* context size to save during system suspend */ 60 #define TEGRA186_SE_CONTEXT_SIZE 3 61 62 static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE]; 63 static unsigned int wake_time[PLATFORM_CORE_COUNT]; 64 65 /* System power down state */ 66 uint32_t tegra186_system_powerdn_state = TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF; 67 68 int32_t tegra_soc_validate_power_state(unsigned int power_state, 69 psci_power_state_t *req_state) 70 { 71 int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK; 72 int cpu = read_mpidr() & MPIDR_CPU_MASK; 73 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 74 75 if (impl == DENVER_IMPL) 76 cpu |= 0x4; 77 78 wake_time[cpu] = (power_state >> TEGRA186_WAKE_TIME_SHIFT) & 79 TEGRA186_WAKE_TIME_MASK; 80 81 /* Sanity check the requested state id */ 82 switch (state_id) { 83 case PSTATE_ID_CORE_IDLE: 84 case PSTATE_ID_CORE_POWERDN: 85 /* 86 * Core powerdown request only for afflvl 0 87 */ 88 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; 89 90 break; 91 92 default: 93 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 94 return PSCI_E_INVALID_PARAMS; 95 } 96 97 return PSCI_E_SUCCESS; 98 } 99 100 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 101 { 102 const plat_local_state_t *pwr_domain_state; 103 unsigned int stateid_afflvl0, stateid_afflvl2; 104 int cpu = read_mpidr() & MPIDR_CPU_MASK; 105 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 106 cpu_context_t *ctx = cm_get_context(NON_SECURE); 107 gp_regs_t *gp_regs = get_gpregs_ctx(ctx); 108 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 109 uint64_t smmu_ctx_base; 110 uint32_t val; 111 112 assert(ctx); 113 assert(gp_regs); 114 115 if (impl == DENVER_IMPL) 116 cpu |= 0x4; 117 118 /* get the state ID */ 119 pwr_domain_state = target_state->pwr_domain_state; 120 stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & 121 TEGRA186_STATE_ID_MASK; 122 stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & 123 TEGRA186_STATE_ID_MASK; 124 125 if (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) { 126 127 /* Prepare for cpu idle */ 128 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, 129 TEGRA_ARI_CORE_C6, wake_time[cpu], 0); 130 131 } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { 132 133 /* Prepare for cpu powerdn */ 134 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, 135 TEGRA_ARI_CORE_C7, wake_time[cpu], 0); 136 137 } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 138 139 /* loop until SC7 is allowed */ 140 do { 141 val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED, 142 TEGRA_ARI_CORE_C7, 143 MCE_CORE_SLEEP_TIME_INFINITE, 144 0); 145 } while (val == 0); 146 147 /* save SE registers */ 148 se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + 149 SE_MUTEX_WATCHDOG_NS_LIMIT); 150 se_regs[1] = mmio_read_32(TEGRA_RNG1_BASE + 151 RNG_MUTEX_WATCHDOG_NS_LIMIT); 152 se_regs[2] = mmio_read_32(TEGRA_PKA1_BASE + 153 PKA_MUTEX_WATCHDOG_NS_LIMIT); 154 155 /* save 'Secure Boot' Processor Feature Config Register */ 156 val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); 157 mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV6, val); 158 159 /* save SMMU context to TZDRAM */ 160 smmu_ctx_base = params_from_bl2->tzdram_base + 161 ((uintptr_t)&__tegra186_cpu_reset_handler_data - 162 (uintptr_t)tegra186_cpu_reset_handler) + 163 TEGRA186_SMMU_CTX_OFFSET; 164 tegra_smmu_save_context((uintptr_t)smmu_ctx_base); 165 166 /* Prepare for system suspend */ 167 write_ctx_reg(gp_regs, CTX_GPREG_X4, 1); 168 write_ctx_reg(gp_regs, CTX_GPREG_X5, 0); 169 write_ctx_reg(gp_regs, CTX_GPREG_X6, 1); 170 (void)mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, 171 TEGRA_ARI_CLUSTER_CC7, 0, TEGRA_ARI_SYSTEM_SC7); 172 173 /* Instruct the MCE to enter system suspend state */ 174 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, 175 TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); 176 177 } else { 178 ERROR("%s: Unknown state id\n", __func__); 179 return PSCI_E_NOT_SUPPORTED; 180 } 181 182 return PSCI_E_SUCCESS; 183 } 184 185 int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) 186 { 187 const plat_local_state_t *pwr_domain_state = 188 target_state->pwr_domain_state; 189 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 190 unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & 191 TEGRA186_STATE_ID_MASK; 192 uint32_t val; 193 194 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 195 /* 196 * The TZRAM loses power when we enter system suspend. To 197 * allow graceful exit from system suspend, we need to copy 198 * BL3-1 over to TZDRAM. 199 */ 200 val = params_from_bl2->tzdram_base + 201 ((uintptr_t)&__tegra186_cpu_reset_handler_end - 202 (uintptr_t)tegra186_cpu_reset_handler); 203 memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, 204 (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); 205 } 206 207 return PSCI_E_SUCCESS; 208 } 209 210 int tegra_soc_pwr_domain_on(u_register_t mpidr) 211 { 212 int target_cpu = mpidr & MPIDR_CPU_MASK; 213 int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> 214 MPIDR_AFFINITY_BITS; 215 216 if (target_cluster > MPIDR_AFFLVL1) { 217 ERROR("%s: unsupported CPU (0x%lx)\n", __func__, mpidr); 218 return PSCI_E_NOT_PRESENT; 219 } 220 221 /* construct the target CPU # */ 222 target_cpu |= (target_cluster << 2); 223 224 mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0); 225 226 return PSCI_E_SUCCESS; 227 } 228 229 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 230 { 231 int state_id = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; 232 cpu_context_t *ctx = cm_get_context(NON_SECURE); 233 gp_regs_t *gp_regs = get_gpregs_ctx(ctx); 234 235 /* 236 * Check if we are exiting from deep sleep and restore SE 237 * context if we are. 238 */ 239 if (state_id == PSTATE_ID_SOC_POWERDN) { 240 mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT, 241 se_regs[0]); 242 mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT, 243 se_regs[1]); 244 mmio_write_32(TEGRA_PKA1_BASE + PKA_MUTEX_WATCHDOG_NS_LIMIT, 245 se_regs[2]); 246 247 /* Init SMMU */ 248 tegra_smmu_init(); 249 250 /* 251 * Reset power state info for the last core doing SC7 entry and exit, 252 * we set deepest power state as CC7 and SC7 for SC7 entry which 253 * may not be requested by non-secure SW which controls idle states. 254 */ 255 write_ctx_reg(gp_regs, CTX_GPREG_X4, 0); 256 write_ctx_reg(gp_regs, CTX_GPREG_X5, 0); 257 write_ctx_reg(gp_regs, CTX_GPREG_X6, 1); 258 (void)mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, 259 TEGRA_ARI_CLUSTER_CC7, 0, TEGRA_ARI_SYSTEM_SC1); 260 } 261 262 return PSCI_E_SUCCESS; 263 } 264 265 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 266 { 267 cpu_context_t *ctx = cm_get_context(NON_SECURE); 268 gp_regs_t *gp_regs = get_gpregs_ctx(ctx); 269 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 270 271 assert(ctx); 272 assert(gp_regs); 273 274 /* Turn off wake_mask */ 275 write_ctx_reg(gp_regs, CTX_GPREG_X4, 0); 276 write_ctx_reg(gp_regs, CTX_GPREG_X5, 0); 277 write_ctx_reg(gp_regs, CTX_GPREG_X6, 1); 278 mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, TEGRA_ARI_CLUSTER_CC7, 279 0, TEGRA_ARI_SYSTEM_SC7); 280 281 /* Disable Denver's DCO operations */ 282 if (impl == DENVER_IMPL) 283 denver_disable_dco(); 284 285 /* Turn off CPU */ 286 return mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7, 287 MCE_CORE_SLEEP_TIME_INFINITE, 0); 288 } 289 290 __dead2 void tegra_soc_prepare_system_off(void) 291 { 292 cpu_context_t *ctx = cm_get_context(NON_SECURE); 293 gp_regs_t *gp_regs = get_gpregs_ctx(ctx); 294 uint32_t val; 295 296 if (tegra186_system_powerdn_state == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) { 297 298 /* power off the entire system */ 299 mce_enter_ccplex_state(tegra186_system_powerdn_state); 300 301 } else if (tegra186_system_powerdn_state == TEGRA_ARI_SYSTEM_SC8) { 302 303 /* loop until other CPUs power down */ 304 do { 305 val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED, 306 TEGRA_ARI_CORE_C7, 307 MCE_CORE_SLEEP_TIME_INFINITE, 308 0); 309 } while (val == 0); 310 311 /* Prepare for quasi power down */ 312 write_ctx_reg(gp_regs, CTX_GPREG_X4, 1); 313 write_ctx_reg(gp_regs, CTX_GPREG_X5, 0); 314 write_ctx_reg(gp_regs, CTX_GPREG_X6, 1); 315 (void)mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, 316 TEGRA_ARI_CLUSTER_CC7, 0, TEGRA_ARI_SYSTEM_SC8); 317 318 /* Enter quasi power down state */ 319 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, 320 TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); 321 322 /* disable GICC */ 323 tegra_gic_cpuif_deactivate(); 324 325 /* power down core */ 326 prepare_cpu_pwr_dwn(); 327 328 } else { 329 ERROR("%s: unsupported power down state (%d)\n", __func__, 330 tegra186_system_powerdn_state); 331 } 332 333 wfi(); 334 335 /* wait for the system to power down */ 336 for (;;) { 337 ; 338 } 339 } 340 341 int tegra_soc_prepare_system_reset(void) 342 { 343 mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT); 344 345 return PSCI_E_SUCCESS; 346 } 347