1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl_common.h> 35 #include <context.h> 36 #include <context_mgmt.h> 37 #include <debug.h> 38 #include <denver.h> 39 #include <mce.h> 40 #include <platform.h> 41 #include <psci.h> 42 #include <smmu.h> 43 #include <string.h> 44 #include <t18x_ari.h> 45 #include <tegra_private.h> 46 47 extern void prepare_cpu_pwr_dwn(void); 48 extern void tegra186_cpu_reset_handler(void); 49 extern uint32_t __tegra186_cpu_reset_handler_end, 50 __tegra186_smmu_context; 51 52 /* state id mask */ 53 #define TEGRA186_STATE_ID_MASK 0xF 54 /* constants to get power state's wake time */ 55 #define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0 56 #define TEGRA186_WAKE_TIME_SHIFT 4 57 /* default core wake mask for CPU_SUSPEND */ 58 #define TEGRA186_CORE_WAKE_MASK 0x180c 59 /* context size to save during system suspend */ 60 #define TEGRA186_SE_CONTEXT_SIZE 3 61 62 static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE]; 63 static struct t18x_psci_percpu_data { 64 unsigned int wake_time; 65 } __aligned(CACHE_WRITEBACK_GRANULE) percpu_data[PLATFORM_CORE_COUNT]; 66 67 /* System power down state */ 68 uint32_t tegra186_system_powerdn_state = TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF; 69 70 int32_t tegra_soc_validate_power_state(unsigned int power_state, 71 psci_power_state_t *req_state) 72 { 73 int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK; 74 int cpu = plat_my_core_pos(); 75 76 /* save the core wake time (in TSC ticks)*/ 77 percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK) 78 << TEGRA186_WAKE_TIME_SHIFT; 79 80 /* 81 * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that 82 * the correct value is read in tegra_soc_pwr_domain_suspend(), which 83 * is called with caches disabled. It is possible to read a stale value 84 * from DRAM in that function, because the L2 cache is not flushed 85 * unless the cluster is entering CC6/CC7. 86 */ 87 clean_dcache_range((uint64_t)&percpu_data[cpu], 88 sizeof(percpu_data[cpu])); 89 90 /* Sanity check the requested state id */ 91 switch (state_id) { 92 case PSTATE_ID_CORE_IDLE: 93 case PSTATE_ID_CORE_POWERDN: 94 95 /* Core powerdown request */ 96 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; 97 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; 98 99 break; 100 101 default: 102 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 103 return PSCI_E_INVALID_PARAMS; 104 } 105 106 return PSCI_E_SUCCESS; 107 } 108 109 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 110 { 111 const plat_local_state_t *pwr_domain_state; 112 unsigned int stateid_afflvl0, stateid_afflvl2; 113 int cpu = plat_my_core_pos(); 114 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 115 mce_cstate_info_t cstate_info = { 0 }; 116 uint64_t smmu_ctx_base; 117 uint32_t val; 118 119 /* get the state ID */ 120 pwr_domain_state = target_state->pwr_domain_state; 121 stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & 122 TEGRA186_STATE_ID_MASK; 123 stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & 124 TEGRA186_STATE_ID_MASK; 125 126 if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) || 127 (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) { 128 129 /* Enter CPU idle/powerdown */ 130 val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? 131 TEGRA_ARI_CORE_C6 : TEGRA_ARI_CORE_C7; 132 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, val, 133 percpu_data[cpu].wake_time, 0); 134 135 } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 136 137 /* save SE registers */ 138 se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + 139 SE_MUTEX_WATCHDOG_NS_LIMIT); 140 se_regs[1] = mmio_read_32(TEGRA_RNG1_BASE + 141 RNG_MUTEX_WATCHDOG_NS_LIMIT); 142 se_regs[2] = mmio_read_32(TEGRA_PKA1_BASE + 143 PKA_MUTEX_WATCHDOG_NS_LIMIT); 144 145 /* save 'Secure Boot' Processor Feature Config Register */ 146 val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); 147 mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV6, val); 148 149 /* save SMMU context to TZDRAM */ 150 smmu_ctx_base = params_from_bl2->tzdram_base + 151 ((uintptr_t)&__tegra186_smmu_context - 152 (uintptr_t)tegra186_cpu_reset_handler); 153 tegra_smmu_save_context((uintptr_t)smmu_ctx_base); 154 155 /* Prepare for system suspend */ 156 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; 157 cstate_info.system = TEGRA_ARI_SYSTEM_SC7; 158 cstate_info.system_state_force = 1; 159 cstate_info.update_wake_mask = 1; 160 mce_update_cstate_info(&cstate_info); 161 162 /* Loop until system suspend is allowed */ 163 do { 164 val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED, 165 TEGRA_ARI_CORE_C7, 166 MCE_CORE_SLEEP_TIME_INFINITE, 167 0); 168 } while (val == 0); 169 170 /* Instruct the MCE to enter system suspend state */ 171 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, 172 TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); 173 } 174 175 return PSCI_E_SUCCESS; 176 } 177 178 /******************************************************************************* 179 * Platform handler to calculate the proper target power level at the 180 * specified affinity level 181 ******************************************************************************/ 182 plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, 183 const plat_local_state_t *states, 184 unsigned int ncpu) 185 { 186 plat_local_state_t target = *states; 187 int cpu = plat_my_core_pos(), ret, cluster_powerdn = 1; 188 int core_pos = read_mpidr() & MPIDR_CPU_MASK; 189 mce_cstate_info_t cstate_info = { 0 }; 190 191 /* get the current core's power state */ 192 target = *(states + core_pos); 193 194 /* CPU suspend */ 195 if (lvl == MPIDR_AFFLVL1 && target == PSTATE_ID_CORE_POWERDN) { 196 197 /* Program default wake mask */ 198 cstate_info.wake_mask = TEGRA186_CORE_WAKE_MASK; 199 cstate_info.update_wake_mask = 1; 200 mce_update_cstate_info(&cstate_info); 201 202 /* Check if CCx state is allowed. */ 203 ret = mce_command_handler(MCE_CMD_IS_CCX_ALLOWED, 204 TEGRA_ARI_CORE_C7, percpu_data[cpu].wake_time, 205 0); 206 if (ret) 207 return PSTATE_ID_CORE_POWERDN; 208 } 209 210 /* CPU off */ 211 if (lvl == MPIDR_AFFLVL1 && target == PLAT_MAX_OFF_STATE) { 212 213 /* find out the number of ON cpus in the cluster */ 214 do { 215 target = *states++; 216 if (target != PLAT_MAX_OFF_STATE) 217 cluster_powerdn = 0; 218 } while (--ncpu); 219 220 /* Enable cluster powerdn from last CPU in the cluster */ 221 if (cluster_powerdn) { 222 223 /* Enable CC7 state and turn off wake mask */ 224 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; 225 cstate_info.update_wake_mask = 1; 226 mce_update_cstate_info(&cstate_info); 227 228 /* Check if CCx state is allowed. */ 229 ret = mce_command_handler(MCE_CMD_IS_CCX_ALLOWED, 230 TEGRA_ARI_CORE_C7, 231 MCE_CORE_SLEEP_TIME_INFINITE, 232 0); 233 if (ret) 234 return PSTATE_ID_CORE_POWERDN; 235 236 } else { 237 238 /* Turn off wake_mask */ 239 cstate_info.update_wake_mask = 1; 240 mce_update_cstate_info(&cstate_info); 241 } 242 } 243 244 /* System Suspend */ 245 if ((lvl == MPIDR_AFFLVL2) || (target == PSTATE_ID_SOC_POWERDN)) 246 return PSTATE_ID_SOC_POWERDN; 247 248 /* default state */ 249 return PSCI_LOCAL_STATE_RUN; 250 } 251 252 int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) 253 { 254 const plat_local_state_t *pwr_domain_state = 255 target_state->pwr_domain_state; 256 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 257 unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & 258 TEGRA186_STATE_ID_MASK; 259 uint64_t val; 260 261 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 262 /* 263 * The TZRAM loses power when we enter system suspend. To 264 * allow graceful exit from system suspend, we need to copy 265 * BL3-1 over to TZDRAM. 266 */ 267 val = params_from_bl2->tzdram_base + 268 ((uintptr_t)&__tegra186_cpu_reset_handler_end - 269 (uintptr_t)tegra186_cpu_reset_handler); 270 memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, 271 (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); 272 } 273 274 return PSCI_E_SUCCESS; 275 } 276 277 int tegra_soc_pwr_domain_on(u_register_t mpidr) 278 { 279 int target_cpu = mpidr & MPIDR_CPU_MASK; 280 int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> 281 MPIDR_AFFINITY_BITS; 282 283 if (target_cluster > MPIDR_AFFLVL1) { 284 ERROR("%s: unsupported CPU (0x%lx)\n", __func__, mpidr); 285 return PSCI_E_NOT_PRESENT; 286 } 287 288 /* construct the target CPU # */ 289 target_cpu |= (target_cluster << 2); 290 291 mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0); 292 293 return PSCI_E_SUCCESS; 294 } 295 296 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 297 { 298 int stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; 299 int stateid_afflvl0 = target_state->pwr_domain_state[MPIDR_AFFLVL0]; 300 mce_cstate_info_t cstate_info = { 0 }; 301 302 /* 303 * Reset power state info for CPUs when onlining, we set 304 * deepest power when offlining a core but that may not be 305 * requested by non-secure sw which controls idle states. It 306 * will re-init this info from non-secure software when the 307 * core come online. 308 */ 309 if (stateid_afflvl0 == PLAT_MAX_OFF_STATE) { 310 311 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC1; 312 cstate_info.update_wake_mask = 1; 313 mce_update_cstate_info(&cstate_info); 314 } 315 316 /* 317 * Check if we are exiting from deep sleep and restore SE 318 * context if we are. 319 */ 320 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 321 322 mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT, 323 se_regs[0]); 324 mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT, 325 se_regs[1]); 326 mmio_write_32(TEGRA_PKA1_BASE + PKA_MUTEX_WATCHDOG_NS_LIMIT, 327 se_regs[2]); 328 329 /* Init SMMU */ 330 tegra_smmu_init(); 331 332 /* 333 * Reset power state info for the last core doing SC7 334 * entry and exit, we set deepest power state as CC7 335 * and SC7 for SC7 entry which may not be requested by 336 * non-secure SW which controls idle states. 337 */ 338 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; 339 cstate_info.system = TEGRA_ARI_SYSTEM_SC1; 340 cstate_info.update_wake_mask = 1; 341 mce_update_cstate_info(&cstate_info); 342 } 343 344 return PSCI_E_SUCCESS; 345 } 346 347 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 348 { 349 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 350 351 /* Disable Denver's DCO operations */ 352 if (impl == DENVER_IMPL) 353 denver_disable_dco(); 354 355 /* Turn off CPU */ 356 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7, 357 MCE_CORE_SLEEP_TIME_INFINITE, 0); 358 359 return PSCI_E_SUCCESS; 360 } 361 362 __dead2 void tegra_soc_prepare_system_off(void) 363 { 364 mce_cstate_info_t cstate_info = { 0 }; 365 uint32_t val; 366 367 if (tegra186_system_powerdn_state == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) { 368 369 /* power off the entire system */ 370 mce_enter_ccplex_state(tegra186_system_powerdn_state); 371 372 } else if (tegra186_system_powerdn_state == TEGRA_ARI_SYSTEM_SC8) { 373 374 /* Prepare for quasi power down */ 375 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; 376 cstate_info.system = TEGRA_ARI_SYSTEM_SC8; 377 cstate_info.system_state_force = 1; 378 cstate_info.update_wake_mask = 1; 379 mce_update_cstate_info(&cstate_info); 380 381 /* loop until other CPUs power down */ 382 do { 383 val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED, 384 TEGRA_ARI_CORE_C7, 385 MCE_CORE_SLEEP_TIME_INFINITE, 386 0); 387 } while (val == 0); 388 389 /* Enter quasi power down state */ 390 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, 391 TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); 392 393 /* disable GICC */ 394 tegra_gic_cpuif_deactivate(); 395 396 /* power down core */ 397 prepare_cpu_pwr_dwn(); 398 399 /* flush L1/L2 data caches */ 400 dcsw_op_all(DCCISW); 401 402 } else { 403 ERROR("%s: unsupported power down state (%d)\n", __func__, 404 tegra186_system_powerdn_state); 405 } 406 407 wfi(); 408 409 /* wait for the system to power down */ 410 for (;;) { 411 ; 412 } 413 } 414 415 int tegra_soc_prepare_system_reset(void) 416 { 417 mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT); 418 419 return PSCI_E_SUCCESS; 420 } 421