1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl_common.h> 35 #include <context.h> 36 #include <context_mgmt.h> 37 #include <debug.h> 38 #include <denver.h> 39 #include <mce.h> 40 #include <psci.h> 41 #include <t18x_ari.h> 42 #include <tegra_private.h> 43 44 /* state id mask */ 45 #define TEGRA186_STATE_ID_MASK 0xF 46 /* constants to get power state's wake time */ 47 #define TEGRA186_WAKE_TIME_MASK 0xFFFFFF 48 #define TEGRA186_WAKE_TIME_SHIFT 4 49 50 static unsigned int wake_time[PLATFORM_CORE_COUNT]; 51 52 int32_t tegra_soc_validate_power_state(unsigned int power_state, 53 psci_power_state_t *req_state) 54 { 55 int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK; 56 int cpu = read_mpidr() & MPIDR_CPU_MASK; 57 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 58 59 if (impl == DENVER_IMPL) 60 cpu |= 0x4; 61 62 wake_time[cpu] = (power_state >> TEGRA186_WAKE_TIME_SHIFT) & 63 TEGRA186_WAKE_TIME_MASK; 64 65 /* Sanity check the requested state id */ 66 switch (state_id) { 67 case PSTATE_ID_CORE_IDLE: 68 case PSTATE_ID_CORE_POWERDN: 69 /* 70 * Core powerdown request only for afflvl 0 71 */ 72 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; 73 74 break; 75 76 default: 77 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 78 return PSCI_E_INVALID_PARAMS; 79 } 80 81 return PSCI_E_SUCCESS; 82 } 83 84 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 85 { 86 const plat_local_state_t *pwr_domain_state; 87 unsigned int stateid_afflvl0; 88 int cpu = read_mpidr() & MPIDR_CPU_MASK; 89 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 90 91 if (impl == DENVER_IMPL) 92 cpu |= 0x4; 93 94 /* get the state ID */ 95 pwr_domain_state = target_state->pwr_domain_state; 96 stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & 97 TEGRA186_STATE_ID_MASK; 98 99 if (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) { 100 101 /* Prepare for cpu idle */ 102 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, 103 TEGRA_ARI_CORE_C6, wake_time[cpu], 0); 104 105 } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { 106 107 /* Prepare for cpu powerdn */ 108 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, 109 TEGRA_ARI_CORE_C7, wake_time[cpu], 0); 110 111 } else { 112 ERROR("%s: Unknown state id\n", __func__); 113 return PSCI_E_NOT_SUPPORTED; 114 } 115 116 return PSCI_E_SUCCESS; 117 } 118 119 int tegra_soc_pwr_domain_on(u_register_t mpidr) 120 { 121 int target_cpu = mpidr & MPIDR_CPU_MASK; 122 int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> 123 MPIDR_AFFINITY_BITS; 124 125 if (target_cluster > MPIDR_AFFLVL1) { 126 ERROR("%s: unsupported CPU (0x%lx)\n", __func__, mpidr); 127 return PSCI_E_NOT_PRESENT; 128 } 129 130 /* construct the target CPU # */ 131 target_cpu |= (target_cluster << 2); 132 133 mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0); 134 135 return PSCI_E_SUCCESS; 136 } 137 138 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 139 { 140 cpu_context_t *ctx = cm_get_context(NON_SECURE); 141 gp_regs_t *gp_regs = get_gpregs_ctx(ctx); 142 143 assert(ctx); 144 assert(gp_regs); 145 146 /* Turn off wake_mask */ 147 write_ctx_reg(gp_regs, CTX_GPREG_X4, 0); 148 write_ctx_reg(gp_regs, CTX_GPREG_X5, 0); 149 write_ctx_reg(gp_regs, CTX_GPREG_X6, 1); 150 mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, TEGRA_ARI_CLUSTER_CC7, 151 0, TEGRA_ARI_SYSTEM_SC7); 152 153 /* Turn off CPU */ 154 return mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7, 155 MCE_CORE_SLEEP_TIME_INFINITE, 0); 156 } 157 158 __dead2 void tegra_soc_prepare_system_off(void) 159 { 160 mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF); 161 } 162 163 int tegra_soc_prepare_system_reset(void) 164 { 165 mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT); 166 167 return PSCI_E_SUCCESS; 168 } 169