1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <context.h> 12 #include <context_mgmt.h> 13 #include <debug.h> 14 #include <denver.h> 15 #include <mce.h> 16 #include <platform.h> 17 #include <psci.h> 18 #include <smmu.h> 19 #include <string.h> 20 #include <t18x_ari.h> 21 #include <tegra_private.h> 22 23 extern void memcpy16(void *dest, const void *src, unsigned int length); 24 25 extern void prepare_cpu_pwr_dwn(void); 26 extern void tegra186_cpu_reset_handler(void); 27 extern uint32_t __tegra186_cpu_reset_handler_end, 28 __tegra186_smmu_context; 29 30 /* state id mask */ 31 #define TEGRA186_STATE_ID_MASK 0xF 32 /* constants to get power state's wake time */ 33 #define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0 34 #define TEGRA186_WAKE_TIME_SHIFT 4 35 /* default core wake mask for CPU_SUSPEND */ 36 #define TEGRA186_CORE_WAKE_MASK 0x180c 37 /* context size to save during system suspend */ 38 #define TEGRA186_SE_CONTEXT_SIZE 3 39 40 static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE]; 41 static struct t18x_psci_percpu_data { 42 unsigned int wake_time; 43 } __aligned(CACHE_WRITEBACK_GRANULE) percpu_data[PLATFORM_CORE_COUNT]; 44 45 /* System power down state */ 46 uint32_t tegra186_system_powerdn_state = TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF; 47 48 int32_t tegra_soc_validate_power_state(unsigned int power_state, 49 psci_power_state_t *req_state) 50 { 51 int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK; 52 int cpu = plat_my_core_pos(); 53 54 /* save the core wake time (in TSC ticks)*/ 55 percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK) 56 << TEGRA186_WAKE_TIME_SHIFT; 57 58 /* 59 * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that 60 * the correct value is read in tegra_soc_pwr_domain_suspend(), which 61 * is called with caches disabled. It is possible to read a stale value 62 * from DRAM in that function, because the L2 cache is not flushed 63 * unless the cluster is entering CC6/CC7. 64 */ 65 clean_dcache_range((uint64_t)&percpu_data[cpu], 66 sizeof(percpu_data[cpu])); 67 68 /* Sanity check the requested state id */ 69 switch (state_id) { 70 case PSTATE_ID_CORE_IDLE: 71 case PSTATE_ID_CORE_POWERDN: 72 73 /* Core powerdown request */ 74 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; 75 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; 76 77 break; 78 79 default: 80 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 81 return PSCI_E_INVALID_PARAMS; 82 } 83 84 return PSCI_E_SUCCESS; 85 } 86 87 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 88 { 89 const plat_local_state_t *pwr_domain_state; 90 unsigned int stateid_afflvl0, stateid_afflvl2; 91 int cpu = plat_my_core_pos(); 92 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 93 mce_cstate_info_t cstate_info = { 0 }; 94 uint64_t smmu_ctx_base; 95 uint32_t val; 96 97 /* get the state ID */ 98 pwr_domain_state = target_state->pwr_domain_state; 99 stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & 100 TEGRA186_STATE_ID_MASK; 101 stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & 102 TEGRA186_STATE_ID_MASK; 103 104 if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) || 105 (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) { 106 107 /* Enter CPU idle/powerdown */ 108 val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? 109 TEGRA_ARI_CORE_C6 : TEGRA_ARI_CORE_C7; 110 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, val, 111 percpu_data[cpu].wake_time, 0); 112 113 } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 114 115 /* save SE registers */ 116 se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + 117 SE_MUTEX_WATCHDOG_NS_LIMIT); 118 se_regs[1] = mmio_read_32(TEGRA_RNG1_BASE + 119 RNG_MUTEX_WATCHDOG_NS_LIMIT); 120 se_regs[2] = mmio_read_32(TEGRA_PKA1_BASE + 121 PKA_MUTEX_WATCHDOG_NS_LIMIT); 122 123 /* save 'Secure Boot' Processor Feature Config Register */ 124 val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); 125 mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV6, val); 126 127 /* save SMMU context to TZDRAM */ 128 smmu_ctx_base = params_from_bl2->tzdram_base + 129 ((uintptr_t)&__tegra186_smmu_context - 130 (uintptr_t)tegra186_cpu_reset_handler); 131 tegra_smmu_save_context((uintptr_t)smmu_ctx_base); 132 133 /* Prepare for system suspend */ 134 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; 135 cstate_info.system = TEGRA_ARI_SYSTEM_SC7; 136 cstate_info.system_state_force = 1; 137 cstate_info.update_wake_mask = 1; 138 mce_update_cstate_info(&cstate_info); 139 140 /* Loop until system suspend is allowed */ 141 do { 142 val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED, 143 TEGRA_ARI_CORE_C7, 144 MCE_CORE_SLEEP_TIME_INFINITE, 145 0); 146 } while (val == 0); 147 148 /* Instruct the MCE to enter system suspend state */ 149 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, 150 TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); 151 } 152 153 return PSCI_E_SUCCESS; 154 } 155 156 /******************************************************************************* 157 * Platform handler to calculate the proper target power level at the 158 * specified affinity level 159 ******************************************************************************/ 160 plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, 161 const plat_local_state_t *states, 162 unsigned int ncpu) 163 { 164 plat_local_state_t target = *states; 165 int cpu = plat_my_core_pos(), ret, cluster_powerdn = 1; 166 int core_pos = read_mpidr() & MPIDR_CPU_MASK; 167 mce_cstate_info_t cstate_info = { 0 }; 168 169 /* get the power state at this level */ 170 if (lvl == MPIDR_AFFLVL1) 171 target = *(states + core_pos); 172 if (lvl == MPIDR_AFFLVL2) 173 target = *(states + cpu); 174 175 /* CPU suspend */ 176 if (lvl == MPIDR_AFFLVL1 && target == PSTATE_ID_CORE_POWERDN) { 177 178 /* Program default wake mask */ 179 cstate_info.wake_mask = TEGRA186_CORE_WAKE_MASK; 180 cstate_info.update_wake_mask = 1; 181 mce_update_cstate_info(&cstate_info); 182 183 /* Check if CCx state is allowed. */ 184 ret = mce_command_handler(MCE_CMD_IS_CCX_ALLOWED, 185 TEGRA_ARI_CORE_C7, percpu_data[cpu].wake_time, 186 0); 187 if (ret) 188 return PSTATE_ID_CORE_POWERDN; 189 } 190 191 /* CPU off */ 192 if (lvl == MPIDR_AFFLVL1 && target == PLAT_MAX_OFF_STATE) { 193 194 /* find out the number of ON cpus in the cluster */ 195 do { 196 target = *states++; 197 if (target != PLAT_MAX_OFF_STATE) 198 cluster_powerdn = 0; 199 } while (--ncpu); 200 201 /* Enable cluster powerdn from last CPU in the cluster */ 202 if (cluster_powerdn) { 203 204 /* Enable CC7 state and turn off wake mask */ 205 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; 206 cstate_info.update_wake_mask = 1; 207 mce_update_cstate_info(&cstate_info); 208 209 /* Check if CCx state is allowed. */ 210 ret = mce_command_handler(MCE_CMD_IS_CCX_ALLOWED, 211 TEGRA_ARI_CORE_C7, 212 MCE_CORE_SLEEP_TIME_INFINITE, 213 0); 214 if (ret) 215 return PSTATE_ID_CORE_POWERDN; 216 217 } else { 218 219 /* Turn off wake_mask */ 220 cstate_info.update_wake_mask = 1; 221 mce_update_cstate_info(&cstate_info); 222 } 223 } 224 225 /* System Suspend */ 226 if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && 227 (target == PSTATE_ID_SOC_POWERDN)) 228 return PSTATE_ID_SOC_POWERDN; 229 230 /* default state */ 231 return PSCI_LOCAL_STATE_RUN; 232 } 233 234 int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) 235 { 236 const plat_local_state_t *pwr_domain_state = 237 target_state->pwr_domain_state; 238 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 239 unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & 240 TEGRA186_STATE_ID_MASK; 241 uint64_t val; 242 243 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 244 /* 245 * The TZRAM loses power when we enter system suspend. To 246 * allow graceful exit from system suspend, we need to copy 247 * BL3-1 over to TZDRAM. 248 */ 249 val = params_from_bl2->tzdram_base + 250 ((uintptr_t)&__tegra186_cpu_reset_handler_end - 251 (uintptr_t)tegra186_cpu_reset_handler); 252 memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, 253 (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); 254 } 255 256 return PSCI_E_SUCCESS; 257 } 258 259 int tegra_soc_pwr_domain_on(u_register_t mpidr) 260 { 261 uint32_t target_cpu = mpidr & MPIDR_CPU_MASK; 262 uint32_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> 263 MPIDR_AFFINITY_BITS; 264 265 if (target_cluster > MPIDR_AFFLVL1) { 266 ERROR("%s: unsupported CPU (0x%lx)\n", __func__, mpidr); 267 return PSCI_E_NOT_PRESENT; 268 } 269 270 /* construct the target CPU # */ 271 target_cpu |= (target_cluster << 2); 272 273 mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0); 274 275 return PSCI_E_SUCCESS; 276 } 277 278 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 279 { 280 int stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; 281 int stateid_afflvl0 = target_state->pwr_domain_state[MPIDR_AFFLVL0]; 282 mce_cstate_info_t cstate_info = { 0 }; 283 284 /* 285 * Reset power state info for CPUs when onlining, we set 286 * deepest power when offlining a core but that may not be 287 * requested by non-secure sw which controls idle states. It 288 * will re-init this info from non-secure software when the 289 * core come online. 290 */ 291 if (stateid_afflvl0 == PLAT_MAX_OFF_STATE) { 292 293 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC1; 294 cstate_info.update_wake_mask = 1; 295 mce_update_cstate_info(&cstate_info); 296 } 297 298 /* 299 * Check if we are exiting from deep sleep and restore SE 300 * context if we are. 301 */ 302 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 303 304 mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT, 305 se_regs[0]); 306 mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT, 307 se_regs[1]); 308 mmio_write_32(TEGRA_PKA1_BASE + PKA_MUTEX_WATCHDOG_NS_LIMIT, 309 se_regs[2]); 310 311 /* Init SMMU */ 312 tegra_smmu_init(); 313 314 /* 315 * Reset power state info for the last core doing SC7 316 * entry and exit, we set deepest power state as CC7 317 * and SC7 for SC7 entry which may not be requested by 318 * non-secure SW which controls idle states. 319 */ 320 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; 321 cstate_info.system = TEGRA_ARI_SYSTEM_SC1; 322 cstate_info.update_wake_mask = 1; 323 mce_update_cstate_info(&cstate_info); 324 } 325 326 return PSCI_E_SUCCESS; 327 } 328 329 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 330 { 331 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 332 333 /* Disable Denver's DCO operations */ 334 if (impl == DENVER_IMPL) 335 denver_disable_dco(); 336 337 /* Turn off CPU */ 338 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7, 339 MCE_CORE_SLEEP_TIME_INFINITE, 0); 340 341 return PSCI_E_SUCCESS; 342 } 343 344 __dead2 void tegra_soc_prepare_system_off(void) 345 { 346 mce_cstate_info_t cstate_info = { 0 }; 347 uint32_t val; 348 349 if (tegra186_system_powerdn_state == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) { 350 351 /* power off the entire system */ 352 mce_enter_ccplex_state(tegra186_system_powerdn_state); 353 354 } else if (tegra186_system_powerdn_state == TEGRA_ARI_SYSTEM_SC8) { 355 356 /* Prepare for quasi power down */ 357 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; 358 cstate_info.system = TEGRA_ARI_SYSTEM_SC8; 359 cstate_info.system_state_force = 1; 360 cstate_info.update_wake_mask = 1; 361 mce_update_cstate_info(&cstate_info); 362 363 /* loop until other CPUs power down */ 364 do { 365 val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED, 366 TEGRA_ARI_CORE_C7, 367 MCE_CORE_SLEEP_TIME_INFINITE, 368 0); 369 } while (val == 0); 370 371 /* Enter quasi power down state */ 372 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, 373 TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); 374 375 /* disable GICC */ 376 tegra_gic_cpuif_deactivate(); 377 378 /* power down core */ 379 prepare_cpu_pwr_dwn(); 380 381 /* flush L1/L2 data caches */ 382 dcsw_op_all(DCCISW); 383 384 } else { 385 ERROR("%s: unsupported power down state (%d)\n", __func__, 386 tegra186_system_powerdn_state); 387 } 388 389 wfi(); 390 391 /* wait for the system to power down */ 392 for (;;) { 393 ; 394 } 395 } 396 397 int tegra_soc_prepare_system_reset(void) 398 { 399 mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT); 400 401 return PSCI_E_SUCCESS; 402 } 403