1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl_common.h> 35 #include <context.h> 36 #include <context_mgmt.h> 37 #include <debug.h> 38 #include <denver.h> 39 #include <mce.h> 40 #include <psci.h> 41 #include <t18x_ari.h> 42 #include <tegra_private.h> 43 44 extern void prepare_cpu_pwr_dwn(void); 45 46 /* state id mask */ 47 #define TEGRA186_STATE_ID_MASK 0xF 48 /* constants to get power state's wake time */ 49 #define TEGRA186_WAKE_TIME_MASK 0xFFFFFF 50 #define TEGRA186_WAKE_TIME_SHIFT 4 51 52 static unsigned int wake_time[PLATFORM_CORE_COUNT]; 53 54 /* System power down state */ 55 uint32_t tegra186_system_powerdn_state = TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF; 56 57 int32_t tegra_soc_validate_power_state(unsigned int power_state, 58 psci_power_state_t *req_state) 59 { 60 int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK; 61 int cpu = read_mpidr() & MPIDR_CPU_MASK; 62 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 63 64 if (impl == DENVER_IMPL) 65 cpu |= 0x4; 66 67 wake_time[cpu] = (power_state >> TEGRA186_WAKE_TIME_SHIFT) & 68 TEGRA186_WAKE_TIME_MASK; 69 70 /* Sanity check the requested state id */ 71 switch (state_id) { 72 case PSTATE_ID_CORE_IDLE: 73 case PSTATE_ID_CORE_POWERDN: 74 /* 75 * Core powerdown request only for afflvl 0 76 */ 77 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; 78 79 break; 80 81 default: 82 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 83 return PSCI_E_INVALID_PARAMS; 84 } 85 86 return PSCI_E_SUCCESS; 87 } 88 89 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 90 { 91 const plat_local_state_t *pwr_domain_state; 92 unsigned int stateid_afflvl0; 93 int cpu = read_mpidr() & MPIDR_CPU_MASK; 94 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 95 96 if (impl == DENVER_IMPL) 97 cpu |= 0x4; 98 99 /* get the state ID */ 100 pwr_domain_state = target_state->pwr_domain_state; 101 stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & 102 TEGRA186_STATE_ID_MASK; 103 104 if (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) { 105 106 /* Prepare for cpu idle */ 107 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, 108 TEGRA_ARI_CORE_C6, wake_time[cpu], 0); 109 110 } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { 111 112 /* Prepare for cpu powerdn */ 113 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, 114 TEGRA_ARI_CORE_C7, wake_time[cpu], 0); 115 116 } else { 117 ERROR("%s: Unknown state id\n", __func__); 118 return PSCI_E_NOT_SUPPORTED; 119 } 120 121 return PSCI_E_SUCCESS; 122 } 123 124 int tegra_soc_pwr_domain_on(u_register_t mpidr) 125 { 126 int target_cpu = mpidr & MPIDR_CPU_MASK; 127 int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> 128 MPIDR_AFFINITY_BITS; 129 130 if (target_cluster > MPIDR_AFFLVL1) { 131 ERROR("%s: unsupported CPU (0x%lx)\n", __func__, mpidr); 132 return PSCI_E_NOT_PRESENT; 133 } 134 135 /* construct the target CPU # */ 136 target_cpu |= (target_cluster << 2); 137 138 mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0); 139 140 return PSCI_E_SUCCESS; 141 } 142 143 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 144 { 145 cpu_context_t *ctx = cm_get_context(NON_SECURE); 146 gp_regs_t *gp_regs = get_gpregs_ctx(ctx); 147 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 148 149 assert(ctx); 150 assert(gp_regs); 151 152 /* Turn off wake_mask */ 153 write_ctx_reg(gp_regs, CTX_GPREG_X4, 0); 154 write_ctx_reg(gp_regs, CTX_GPREG_X5, 0); 155 write_ctx_reg(gp_regs, CTX_GPREG_X6, 1); 156 mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, TEGRA_ARI_CLUSTER_CC7, 157 0, TEGRA_ARI_SYSTEM_SC7); 158 159 /* Disable Denver's DCO operations */ 160 if (impl == DENVER_IMPL) 161 denver_disable_dco(); 162 163 /* Turn off CPU */ 164 return mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7, 165 MCE_CORE_SLEEP_TIME_INFINITE, 0); 166 } 167 168 __dead2 void tegra_soc_prepare_system_off(void) 169 { 170 cpu_context_t *ctx = cm_get_context(NON_SECURE); 171 gp_regs_t *gp_regs = get_gpregs_ctx(ctx); 172 uint32_t val; 173 174 if (tegra186_system_powerdn_state == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) { 175 176 /* power off the entire system */ 177 mce_enter_ccplex_state(tegra186_system_powerdn_state); 178 179 } else if (tegra186_system_powerdn_state == TEGRA_ARI_SYSTEM_SC8) { 180 181 /* loop until other CPUs power down */ 182 do { 183 val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED, 184 TEGRA_ARI_CORE_C7, 185 MCE_CORE_SLEEP_TIME_INFINITE, 186 0); 187 } while (val == 0); 188 189 /* Prepare for quasi power down */ 190 write_ctx_reg(gp_regs, CTX_GPREG_X4, 1); 191 write_ctx_reg(gp_regs, CTX_GPREG_X5, 0); 192 write_ctx_reg(gp_regs, CTX_GPREG_X6, 1); 193 (void)mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, 194 TEGRA_ARI_CLUSTER_CC7, 0, TEGRA_ARI_SYSTEM_SC8); 195 196 /* Enter quasi power down state */ 197 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, 198 TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); 199 200 /* disable GICC */ 201 tegra_gic_cpuif_deactivate(); 202 203 /* power down core */ 204 prepare_cpu_pwr_dwn(); 205 206 } else { 207 ERROR("%s: unsupported power down state (%d)\n", __func__, 208 tegra186_system_powerdn_state); 209 } 210 211 wfi(); 212 213 /* wait for the system to power down */ 214 for (;;) { 215 ; 216 } 217 } 218 219 int tegra_soc_prepare_system_reset(void) 220 { 221 mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT); 222 223 return PSCI_E_SUCCESS; 224 } 225