1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <common/bl_common.h> 10 11 #include <mce.h> 12 #include <memctrl_v2.h> 13 #include <tegra186_private.h> 14 #include <tegra_mc_def.h> 15 #include <tegra_platform.h> 16 #include <tegra_private.h> 17 18 extern uint64_t tegra_bl31_phys_base; 19 20 /******************************************************************************* 21 * Array to hold stream_id override config register offsets 22 ******************************************************************************/ 23 const static uint32_t tegra186_streamid_override_regs[] = { 24 MC_STREAMID_OVERRIDE_CFG_SDMMCRA, 25 MC_STREAMID_OVERRIDE_CFG_SDMMCRAA, 26 MC_STREAMID_OVERRIDE_CFG_SDMMCR, 27 MC_STREAMID_OVERRIDE_CFG_SDMMCRAB, 28 MC_STREAMID_OVERRIDE_CFG_SDMMCWA, 29 MC_STREAMID_OVERRIDE_CFG_SDMMCWAA, 30 MC_STREAMID_OVERRIDE_CFG_SDMMCW, 31 MC_STREAMID_OVERRIDE_CFG_SDMMCWAB, 32 }; 33 34 /******************************************************************************* 35 * Array to hold the security configs for stream IDs 36 ******************************************************************************/ 37 const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = { 38 mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE), 39 mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, DISABLE), 40 mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, DISABLE), 41 mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, DISABLE), 42 mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE), 43 mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, DISABLE), 44 mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 45 mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, DISABLE), 46 mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE), 47 mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, DISABLE), 48 mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 49 mc_make_sec_cfg(GPUSWR2, SECURE, NO_OVERRIDE, DISABLE), 50 mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, DISABLE), 51 mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, DISABLE), 52 mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, DISABLE), 53 mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 54 mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, DISABLE), 55 mc_make_sec_cfg(SDMMCWAA, NON_SECURE, OVERRIDE, DISABLE), 56 mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, DISABLE), 57 mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, DISABLE), 58 mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, DISABLE), 59 mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, DISABLE), 60 mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, DISABLE), 61 mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE), 62 mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 63 mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 64 mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, DISABLE), 65 mc_make_sec_cfg(ISPWA, NON_SECURE, OVERRIDE, ENABLE), 66 mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, DISABLE), 67 mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE), 68 mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 69 mc_make_sec_cfg(SDMMCRAA, NON_SECURE, OVERRIDE, DISABLE), 70 mc_make_sec_cfg(VIW, NON_SECURE, OVERRIDE, ENABLE), 71 mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE), 72 mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, DISABLE), 73 mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 74 mc_make_sec_cfg(ISPRA, NON_SECURE, OVERRIDE, ENABLE), 75 mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 76 mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE), 77 mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 78 mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, DISABLE), 79 mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, DISABLE), 80 mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 81 mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, DISABLE), 82 mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, DISABLE), 83 mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 84 mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 85 mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, DISABLE), 86 mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, DISABLE), 87 mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE), 88 mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 89 mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 90 mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, DISABLE), 91 mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, DISABLE), 92 mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 93 mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, DISABLE), 94 mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, DISABLE), 95 mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, DISABLE), 96 mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, DISABLE), 97 mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, DISABLE), 98 mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, DISABLE), 99 mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, DISABLE), 100 mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, DISABLE), 101 mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, DISABLE), 102 mc_make_sec_cfg(GPUSWR, SECURE, NO_OVERRIDE, DISABLE), 103 mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, DISABLE), 104 mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE), 105 mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE), 106 mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE), 107 mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, DISABLE), 108 mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, DISABLE), 109 mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE), 110 }; 111 112 /******************************************************************************* 113 * Array to hold the transaction override configs 114 ******************************************************************************/ 115 const static mc_txn_override_cfg_t tegra186_txn_override_cfgs[] = { 116 mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR), 117 mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR), 118 mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR), 119 mc_make_txn_override_cfg(SDMMCWAA, CGID_TAG_ADR), 120 mc_make_txn_override_cfg(MPCOREW, CGID_TAG_ADR), 121 mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR), 122 mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR), 123 mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR), 124 mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR), 125 mc_make_txn_override_cfg(GPUSWR, CGID_TAG_ADR), 126 mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR), 127 mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR), 128 mc_make_txn_override_cfg(GPUSWR2, CGID_TAG_ADR), 129 mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR), 130 mc_make_txn_override_cfg(AONW, CGID_TAG_ADR), 131 mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR), 132 mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR), 133 mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR), 134 mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR), 135 mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR), 136 mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR), 137 mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR), 138 mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR), 139 mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR), 140 mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR), 141 mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR), 142 mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR), 143 mc_make_txn_override_cfg(APEW, CGID_TAG_ADR), 144 mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR), 145 mc_make_txn_override_cfg(AFIW, CGID_TAG_ADR), 146 mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR), 147 }; 148 149 static void tegra186_memctrl_reconfig_mss_clients(void) 150 { 151 #if ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS 152 uint32_t val, wdata_0, wdata_1; 153 154 /* 155 * Assert Memory Controller's HOTRESET_FLUSH_ENABLE signal for 156 * boot and strongly ordered MSS clients to flush existing memory 157 * traffic and stall future requests. 158 */ 159 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0); 160 assert(val == MC_CLIENT_HOTRESET_CTRL0_RESET_VAL); 161 162 wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB | 163 MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB | 164 MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB | 165 MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB | 166 MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB; 167 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); 168 169 /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ 170 do { 171 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0); 172 } while ((val & wdata_0) != wdata_0); 173 174 /* Wait one more time due to SW WAR for known legacy issue */ 175 do { 176 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0); 177 } while ((val & wdata_0) != wdata_0); 178 179 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1); 180 assert(val == MC_CLIENT_HOTRESET_CTRL1_RESET_VAL); 181 182 wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB | 183 MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB | 184 MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB | 185 MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB | 186 MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB | 187 MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB | 188 MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB | 189 MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB | 190 MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB | 191 MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB; 192 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); 193 194 /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ 195 do { 196 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1); 197 } while ((val & wdata_1) != wdata_1); 198 199 /* Wait one more time due to SW WAR for known legacy issue */ 200 do { 201 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1); 202 } while ((val & wdata_1) != wdata_1); 203 204 /* 205 * Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and 206 * strongly ordered MSS clients. ROC needs to be single point 207 * of control on overriding the memory type. So, remove TSA's 208 * memtype override. 209 * 210 * MC clients with default SO_DEV override still enabled at TSA: 211 * AONW, BPMPW, SCEW, APEW 212 */ 213 mc_set_tsa_passthrough(AFIW); 214 mc_set_tsa_passthrough(HDAW); 215 mc_set_tsa_passthrough(SATAW); 216 mc_set_tsa_passthrough(XUSB_HOSTW); 217 mc_set_tsa_passthrough(XUSB_DEVW); 218 mc_set_tsa_passthrough(SDMMCWAB); 219 mc_set_tsa_passthrough(APEDMAW); 220 mc_set_tsa_passthrough(SESWR); 221 mc_set_tsa_passthrough(ETRW); 222 mc_set_tsa_passthrough(AXISW); 223 mc_set_tsa_passthrough(EQOSW); 224 mc_set_tsa_passthrough(UFSHCW); 225 mc_set_tsa_passthrough(BPMPDMAW); 226 mc_set_tsa_passthrough(AONDMAW); 227 mc_set_tsa_passthrough(SCEDMAW); 228 229 /* Parker has no IO Coherency support and need the following: 230 * Ordered MC Clients on Parker are AFI, EQOS, SATA, XUSB. 231 * ISO clients(DISP, VI, EQOS) should never snoop caches and 232 * don't need ROC/PCFIFO ordering. 233 * ISO clients(EQOS) that need ordering should use PCFIFO ordering 234 * and bypass ROC ordering by using FORCE_NON_COHERENT path. 235 * FORCE_NON_COHERENT/FORCE_COHERENT config take precedence 236 * over SMMU attributes. 237 * Force all Normal memory transactions from ISO and non-ISO to be 238 * non-coherent(bypass ROC, avoid cache snoop to avoid perf hit). 239 * Force the SO_DEV transactions from ordered ISO clients(EQOS) to 240 * non-coherent path and enable MC PCFIFO interlock for ordering. 241 * Force the SO_DEV transactions from ordered non-ISO clients (PCIe, 242 * XUSB, SATA) to coherent so that the transactions are 243 * ordered by ROC. 244 * PCFIFO ensure write ordering. 245 * Read after Write ordering is maintained/enforced by MC clients. 246 * Clients that need PCIe type write ordering must 247 * go through ROC ordering. 248 * Ordering enable for Read clients is not necessary. 249 * R5's and A9 would get necessary ordering from AXI and 250 * don't need ROC ordering enable: 251 * - MMIO ordering is through dev mapping and MMIO 252 * accesses bypass SMMU. 253 * - Normal memory is accessed through SMMU and ordering is 254 * ensured by client and AXI. 255 * - Ack point for Normal memory is WCAM in MC. 256 * - MMIO's can be early acked and AXI ensures dev memory ordering, 257 * Client ensures read/write direction change ordering. 258 * - See Bug 200312466 for more details. 259 * 260 * CGID_TAG_ADR is only present from T186 A02. As this code is common 261 * between A01 and A02, tegra_memctrl_set_overrides() programs 262 * CGID_TAG_ADR for the necessary clients on A02. 263 */ 264 mc_set_txn_override(HDAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 265 mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 266 mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 267 mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 268 mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 269 mc_set_txn_override(NVJPGSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 270 mc_set_txn_override(ISPRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 271 mc_set_txn_override(SDMMCWAA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 272 mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 273 mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 274 mc_set_txn_override(GPUSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 275 mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 276 mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 277 mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 278 mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 279 /* See bug 200131110 comment #35*/ 280 mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 281 mc_set_txn_override(NVENCSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 282 mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 283 mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 284 mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 285 mc_set_txn_override(VIW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 286 mc_set_txn_override(SDMMCRAA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 287 mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 288 mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 289 mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 290 mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 291 mc_set_txn_override(GPUSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 292 mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 293 mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT); 294 mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 295 mc_set_txn_override(GPUSRD2, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 296 mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 297 mc_set_txn_override(GPUSWR2, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 298 mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 299 /* See bug 200131110 comment #35*/ 300 mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 301 mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 302 mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 303 mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 304 mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 305 mc_set_txn_override(NVJPGSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 306 mc_set_txn_override(NVDECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 307 mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 308 mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 309 mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 310 mc_set_txn_override(NVDECSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 311 mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 312 mc_set_txn_override(ISPWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 313 mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 314 mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 315 mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 316 mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); 317 mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 318 mc_set_txn_override(HDAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 319 mc_set_txn_override(NVDECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 320 mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 321 mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 322 mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT); 323 mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 324 mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 325 mc_set_txn_override(NVENCSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 326 /* See bug 200131110 comment #35 */ 327 mc_set_txn_override(AFIR, CGID_TAG_DEFAULT, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 328 mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 329 mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 330 mc_set_txn_override(NVDISPLAYR1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 331 mc_set_txn_override(ISPWB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 332 mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 333 mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 334 mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 335 mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT); 336 mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 337 /* 338 * See bug 200131110 comment #35 - there are no normal requests 339 * and AWID for SO/DEV requests is hardcoded in RTL for a 340 * particular PCIE controller 341 */ 342 mc_set_txn_override(AFIW, CGID_TAG_DEFAULT, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_COHERENT); 343 mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); 344 345 /* 346 * At this point, ordering can occur at ROC. So, remove PCFIFO's 347 * control over ordering requests. 348 * 349 * Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for 350 * boot and strongly ordered MSS clients 351 */ 352 val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL & 353 mc_set_pcfifo_unordered_boot_so_mss(1, AFIW) & 354 mc_set_pcfifo_unordered_boot_so_mss(1, HDAW) & 355 mc_set_pcfifo_unordered_boot_so_mss(1, SATAW); 356 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, val); 357 358 val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL & 359 mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) & 360 mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_DEVW); 361 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, val); 362 363 val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL & 364 mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB); 365 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, val); 366 367 val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL & 368 mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) & 369 mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) & 370 mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) & 371 mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) & 372 mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) & 373 mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) & 374 mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW); 375 /* EQOSW is the only client that has PCFIFO order enabled. */ 376 val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW); 377 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, val); 378 379 val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL & 380 mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW); 381 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, val); 382 383 /* 384 * Deassert HOTRESET FLUSH_ENABLE for boot and strongly ordered MSS 385 * clients to allow memory traffic from all clients to start passing 386 * through ROC 387 */ 388 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0); 389 assert(val == wdata_0); 390 391 wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL; 392 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); 393 394 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1); 395 assert(val == wdata_1); 396 397 wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL; 398 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); 399 400 #endif 401 } 402 403 static void tegra186_memctrl_set_overrides(void) 404 { 405 const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings(); 406 const mc_txn_override_cfg_t *mc_txn_override_cfgs; 407 uint32_t num_txn_override_cfgs; 408 uint32_t i, val; 409 410 /* Get the settings from the platform */ 411 assert(plat_mc_settings != NULL); 412 mc_txn_override_cfgs = plat_mc_settings->txn_override_cfg; 413 num_txn_override_cfgs = plat_mc_settings->num_txn_override_cfgs; 414 415 /* 416 * Set the MC_TXN_OVERRIDE registers for write clients. 417 */ 418 if ((tegra_chipid_is_t186()) && 419 (!tegra_platform_is_silicon() || 420 (tegra_platform_is_silicon() && (tegra_get_chipid_minor() == 1U)))) { 421 422 /* 423 * GPU and NVENC settings for Tegra186 simulation and 424 * Silicon rev. A01 425 */ 426 val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR); 427 val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK; 428 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR, 429 val | MC_TXN_OVERRIDE_CGID_TAG_ZERO); 430 431 val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2); 432 val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK; 433 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2, 434 val | MC_TXN_OVERRIDE_CGID_TAG_ZERO); 435 436 val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR); 437 val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK; 438 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR, 439 val | MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID); 440 441 } else { 442 443 /* 444 * Settings for Tegra186 silicon rev. A02 and onwards. 445 */ 446 for (i = 0; i < num_txn_override_cfgs; i++) { 447 val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset); 448 val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK; 449 tegra_mc_write_32(mc_txn_override_cfgs[i].offset, 450 val | mc_txn_override_cfgs[i].cgid_tag); 451 } 452 } 453 } 454 455 456 /******************************************************************************* 457 * Array to hold MC context for Tegra186 458 ******************************************************************************/ 459 static __attribute__((aligned(16))) mc_regs_t tegra186_mc_context[] = { 460 _START_OF_TABLE_, 461 mc_make_sid_security_cfg(SCEW), 462 mc_make_sid_security_cfg(AFIR), 463 mc_make_sid_security_cfg(NVDISPLAYR1), 464 mc_make_sid_security_cfg(XUSB_DEVR), 465 mc_make_sid_security_cfg(VICSRD1), 466 mc_make_sid_security_cfg(NVENCSWR), 467 mc_make_sid_security_cfg(TSECSRDB), 468 mc_make_sid_security_cfg(AXISW), 469 mc_make_sid_security_cfg(SDMMCWAB), 470 mc_make_sid_security_cfg(AONDMAW), 471 mc_make_sid_security_cfg(GPUSWR2), 472 mc_make_sid_security_cfg(SATAW), 473 mc_make_sid_security_cfg(UFSHCW), 474 mc_make_sid_security_cfg(AFIW), 475 mc_make_sid_security_cfg(SDMMCR), 476 mc_make_sid_security_cfg(SCEDMAW), 477 mc_make_sid_security_cfg(UFSHCR), 478 mc_make_sid_security_cfg(SDMMCWAA), 479 mc_make_sid_security_cfg(APEDMAW), 480 mc_make_sid_security_cfg(SESWR), 481 mc_make_sid_security_cfg(MPCORER), 482 mc_make_sid_security_cfg(PTCR), 483 mc_make_sid_security_cfg(BPMPW), 484 mc_make_sid_security_cfg(ETRW), 485 mc_make_sid_security_cfg(GPUSRD), 486 mc_make_sid_security_cfg(VICSWR), 487 mc_make_sid_security_cfg(SCEDMAR), 488 mc_make_sid_security_cfg(HDAW), 489 mc_make_sid_security_cfg(ISPWA), 490 mc_make_sid_security_cfg(EQOSW), 491 mc_make_sid_security_cfg(XUSB_HOSTW), 492 mc_make_sid_security_cfg(TSECSWR), 493 mc_make_sid_security_cfg(SDMMCRAA), 494 mc_make_sid_security_cfg(APER), 495 mc_make_sid_security_cfg(VIW), 496 mc_make_sid_security_cfg(APEW), 497 mc_make_sid_security_cfg(AXISR), 498 mc_make_sid_security_cfg(SDMMCW), 499 mc_make_sid_security_cfg(BPMPDMAW), 500 mc_make_sid_security_cfg(ISPRA), 501 mc_make_sid_security_cfg(NVDECSWR), 502 mc_make_sid_security_cfg(XUSB_DEVW), 503 mc_make_sid_security_cfg(NVDECSRD), 504 mc_make_sid_security_cfg(MPCOREW), 505 mc_make_sid_security_cfg(NVDISPLAYR), 506 mc_make_sid_security_cfg(BPMPDMAR), 507 mc_make_sid_security_cfg(NVJPGSWR), 508 mc_make_sid_security_cfg(NVDECSRD1), 509 mc_make_sid_security_cfg(TSECSRD), 510 mc_make_sid_security_cfg(NVJPGSRD), 511 mc_make_sid_security_cfg(SDMMCWA), 512 mc_make_sid_security_cfg(SCER), 513 mc_make_sid_security_cfg(XUSB_HOSTR), 514 mc_make_sid_security_cfg(VICSRD), 515 mc_make_sid_security_cfg(AONDMAR), 516 mc_make_sid_security_cfg(AONW), 517 mc_make_sid_security_cfg(SDMMCRA), 518 mc_make_sid_security_cfg(HOST1XDMAR), 519 mc_make_sid_security_cfg(EQOSR), 520 mc_make_sid_security_cfg(SATAR), 521 mc_make_sid_security_cfg(BPMPR), 522 mc_make_sid_security_cfg(HDAR), 523 mc_make_sid_security_cfg(SDMMCRAB), 524 mc_make_sid_security_cfg(ETRR), 525 mc_make_sid_security_cfg(AONR), 526 mc_make_sid_security_cfg(APEDMAR), 527 mc_make_sid_security_cfg(SESRD), 528 mc_make_sid_security_cfg(NVENCSRD), 529 mc_make_sid_security_cfg(GPUSWR), 530 mc_make_sid_security_cfg(TSECSWRB), 531 mc_make_sid_security_cfg(ISPWB), 532 mc_make_sid_security_cfg(GPUSRD2), 533 mc_make_sid_override_cfg(APER), 534 mc_make_sid_override_cfg(VICSRD), 535 mc_make_sid_override_cfg(NVENCSRD), 536 mc_make_sid_override_cfg(NVJPGSWR), 537 mc_make_sid_override_cfg(AONW), 538 mc_make_sid_override_cfg(BPMPR), 539 mc_make_sid_override_cfg(BPMPW), 540 mc_make_sid_override_cfg(HDAW), 541 mc_make_sid_override_cfg(NVDISPLAYR1), 542 mc_make_sid_override_cfg(APEDMAR), 543 mc_make_sid_override_cfg(AFIR), 544 mc_make_sid_override_cfg(AXISR), 545 mc_make_sid_override_cfg(VICSRD1), 546 mc_make_sid_override_cfg(TSECSRD), 547 mc_make_sid_override_cfg(BPMPDMAW), 548 mc_make_sid_override_cfg(MPCOREW), 549 mc_make_sid_override_cfg(XUSB_HOSTR), 550 mc_make_sid_override_cfg(GPUSWR), 551 mc_make_sid_override_cfg(XUSB_DEVR), 552 mc_make_sid_override_cfg(UFSHCW), 553 mc_make_sid_override_cfg(XUSB_HOSTW), 554 mc_make_sid_override_cfg(SDMMCWAB), 555 mc_make_sid_override_cfg(SATAW), 556 mc_make_sid_override_cfg(SCEDMAR), 557 mc_make_sid_override_cfg(HOST1XDMAR), 558 mc_make_sid_override_cfg(SDMMCWA), 559 mc_make_sid_override_cfg(APEDMAW), 560 mc_make_sid_override_cfg(SESWR), 561 mc_make_sid_override_cfg(AXISW), 562 mc_make_sid_override_cfg(AONDMAW), 563 mc_make_sid_override_cfg(TSECSWRB), 564 mc_make_sid_override_cfg(MPCORER), 565 mc_make_sid_override_cfg(ISPWB), 566 mc_make_sid_override_cfg(AONR), 567 mc_make_sid_override_cfg(BPMPDMAR), 568 mc_make_sid_override_cfg(HDAR), 569 mc_make_sid_override_cfg(SDMMCRA), 570 mc_make_sid_override_cfg(ETRW), 571 mc_make_sid_override_cfg(GPUSWR2), 572 mc_make_sid_override_cfg(EQOSR), 573 mc_make_sid_override_cfg(TSECSWR), 574 mc_make_sid_override_cfg(ETRR), 575 mc_make_sid_override_cfg(NVDECSRD), 576 mc_make_sid_override_cfg(TSECSRDB), 577 mc_make_sid_override_cfg(SDMMCRAA), 578 mc_make_sid_override_cfg(NVDECSRD1), 579 mc_make_sid_override_cfg(SDMMCR), 580 mc_make_sid_override_cfg(NVJPGSRD), 581 mc_make_sid_override_cfg(SCEDMAW), 582 mc_make_sid_override_cfg(SDMMCWAA), 583 mc_make_sid_override_cfg(APEW), 584 mc_make_sid_override_cfg(AONDMAR), 585 mc_make_sid_override_cfg(PTCR), 586 mc_make_sid_override_cfg(SCER), 587 mc_make_sid_override_cfg(ISPRA), 588 mc_make_sid_override_cfg(ISPWA), 589 mc_make_sid_override_cfg(VICSWR), 590 mc_make_sid_override_cfg(SESRD), 591 mc_make_sid_override_cfg(SDMMCW), 592 mc_make_sid_override_cfg(SDMMCRAB), 593 mc_make_sid_override_cfg(EQOSW), 594 mc_make_sid_override_cfg(GPUSRD2), 595 mc_make_sid_override_cfg(SCEW), 596 mc_make_sid_override_cfg(GPUSRD), 597 mc_make_sid_override_cfg(NVDECSWR), 598 mc_make_sid_override_cfg(XUSB_DEVW), 599 mc_make_sid_override_cfg(SATAR), 600 mc_make_sid_override_cfg(NVDISPLAYR), 601 mc_make_sid_override_cfg(VIW), 602 mc_make_sid_override_cfg(UFSHCR), 603 mc_make_sid_override_cfg(NVENCSWR), 604 mc_make_sid_override_cfg(AFIW), 605 mc_smmu_bypass_cfg, /* TBU settings */ 606 _END_OF_TABLE_, 607 }; 608 609 /******************************************************************************* 610 * Handler to return the pointer to the MC's context struct 611 ******************************************************************************/ 612 static mc_regs_t *tegra186_get_mc_system_suspend_ctx(void) 613 { 614 /* index of _END_OF_TABLE_ */ 615 tegra186_mc_context[0].val = (uint32_t)(ARRAY_SIZE(tegra186_mc_context)) - 1U; 616 617 return tegra186_mc_context; 618 } 619 620 /******************************************************************************* 621 * Struct to hold the memory controller settings 622 ******************************************************************************/ 623 static tegra_mc_settings_t tegra186_mc_settings = { 624 .streamid_override_cfg = tegra186_streamid_override_regs, 625 .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_streamid_override_regs), 626 .streamid_security_cfg = tegra186_streamid_sec_cfgs, 627 .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra186_streamid_sec_cfgs), 628 .txn_override_cfg = tegra186_txn_override_cfgs, 629 .num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_txn_override_cfgs), 630 .reconfig_mss_clients = tegra186_memctrl_reconfig_mss_clients, 631 .set_txn_overrides = tegra186_memctrl_set_overrides, 632 .get_mc_system_suspend_ctx = tegra186_get_mc_system_suspend_ctx, 633 }; 634 635 /******************************************************************************* 636 * Handler to return the pointer to the memory controller's settings struct 637 ******************************************************************************/ 638 tegra_mc_settings_t *tegra_get_mc_settings(void) 639 { 640 return &tegra186_mc_settings; 641 } 642 643 /******************************************************************************* 644 * Handler to program the scratch registers with TZDRAM settings for the 645 * resume firmware 646 ******************************************************************************/ 647 void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) 648 { 649 uint32_t val; 650 651 /* 652 * Setup the Memory controller to allow only secure accesses to 653 * the TZDRAM carveout 654 */ 655 INFO("Configuring TrustZone DRAM Memory Carveout\n"); 656 657 tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base); 658 tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32)); 659 tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); 660 661 /* 662 * When TZ encryption is enabled, we need to setup TZDRAM 663 * before CPU accesses TZ Carveout, else CPU will fetch 664 * non-decrypted data. So save TZDRAM setting for SC7 resume 665 * FW to restore. 666 * 667 * Scratch registers map: 668 * RSV55_0 = CFG1[12:0] | CFG0[31:20] 669 * RSV55_1 = CFG3[1:0] 670 */ 671 val = tegra_mc_read_32(MC_SECURITY_CFG1_0) & MC_SECURITY_SIZE_MB_MASK; 672 val |= tegra_mc_read_32(MC_SECURITY_CFG0_0) & MC_SECURITY_BOM_MASK; 673 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_LO, val); 674 675 val = tegra_mc_read_32(MC_SECURITY_CFG3_0) & MC_SECURITY_BOM_HI_MASK; 676 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_HI, val); 677 678 /* 679 * MCE propagates the security configuration values across the 680 * CCPLEX. 681 */ 682 (void)mce_update_gsc_tzdram(); 683 } 684