xref: /rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/plat_memctrl.c (revision 06803cfd020b1c953b9a4a32fbfa401b3f4f5491)
1*06803cfdSPritesh Raithatha /*
2*06803cfdSPritesh Raithatha  * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3*06803cfdSPritesh Raithatha  *
4*06803cfdSPritesh Raithatha  * Redistribution and use in source and binary forms, with or without
5*06803cfdSPritesh Raithatha  * modification, are permitted provided that the following conditions are met:
6*06803cfdSPritesh Raithatha  *
7*06803cfdSPritesh Raithatha  * Redistributions of source code must retain the above copyright notice, this
8*06803cfdSPritesh Raithatha  * list of conditions and the following disclaimer.
9*06803cfdSPritesh Raithatha  *
10*06803cfdSPritesh Raithatha  * Redistributions in binary form must reproduce the above copyright notice,
11*06803cfdSPritesh Raithatha  * this list of conditions and the following disclaimer in the documentation
12*06803cfdSPritesh Raithatha  * and/or other materials provided with the distribution.
13*06803cfdSPritesh Raithatha  *
14*06803cfdSPritesh Raithatha  * Neither the name of ARM nor the names of its contributors may be used
15*06803cfdSPritesh Raithatha  * to endorse or promote products derived from this software without specific
16*06803cfdSPritesh Raithatha  * prior written permission.
17*06803cfdSPritesh Raithatha  *
18*06803cfdSPritesh Raithatha  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19*06803cfdSPritesh Raithatha  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20*06803cfdSPritesh Raithatha  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21*06803cfdSPritesh Raithatha  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22*06803cfdSPritesh Raithatha  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23*06803cfdSPritesh Raithatha  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24*06803cfdSPritesh Raithatha  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25*06803cfdSPritesh Raithatha  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26*06803cfdSPritesh Raithatha  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27*06803cfdSPritesh Raithatha  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28*06803cfdSPritesh Raithatha  * POSSIBILITY OF SUCH DAMAGE.
29*06803cfdSPritesh Raithatha  */
30*06803cfdSPritesh Raithatha 
31*06803cfdSPritesh Raithatha #include <bl_common.h>
32*06803cfdSPritesh Raithatha #include <memctrl_v2.h>
33*06803cfdSPritesh Raithatha 
34*06803cfdSPritesh Raithatha /*******************************************************************************
35*06803cfdSPritesh Raithatha  * Array to hold stream_id override config register offsets
36*06803cfdSPritesh Raithatha  ******************************************************************************/
37*06803cfdSPritesh Raithatha const static uint32_t tegra186_streamid_override_regs[] = {
38*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_PTCR,
39*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_AFIR,
40*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_HDAR,
41*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
42*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
43*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_SATAR,
44*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_MPCORER,
45*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
46*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_AFIW,
47*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_HDAW,
48*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_MPCOREW,
49*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_SATAW,
50*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_ISPRA,
51*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_ISPWA,
52*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_ISPWB,
53*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
54*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
55*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
56*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
57*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_TSECSRD,
58*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_TSECSWR,
59*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_GPUSRD,
60*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_GPUSWR,
61*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
62*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_SDMMCRAA,
63*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_SDMMCR,
64*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
65*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
66*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_SDMMCWAA,
67*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_SDMMCW,
68*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
69*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_VICSRD,
70*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_VICSWR,
71*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_VIW,
72*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
73*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
74*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_APER,
75*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_APEW,
76*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
77*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
78*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_SESRD,
79*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_SESWR,
80*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_ETRR,
81*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_ETRW,
82*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
83*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
84*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_GPUSRD2,
85*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_GPUSWR2,
86*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_AXISR,
87*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_AXISW,
88*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_EQOSR,
89*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_EQOSW,
90*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_UFSHCR,
91*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_UFSHCW,
92*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
93*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_BPMPR,
94*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_BPMPW,
95*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
96*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
97*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_AONR,
98*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_AONW,
99*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_AONDMAR,
100*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_AONDMAW,
101*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_SCER,
102*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_SCEW,
103*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
104*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
105*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_APEDMAR,
106*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_APEDMAW,
107*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
108*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_VICSRD1,
109*06803cfdSPritesh Raithatha 	MC_STREAMID_OVERRIDE_CFG_NVDECSRD1
110*06803cfdSPritesh Raithatha };
111*06803cfdSPritesh Raithatha 
112*06803cfdSPritesh Raithatha /*******************************************************************************
113*06803cfdSPritesh Raithatha  * Array to hold the security configs for stream IDs
114*06803cfdSPritesh Raithatha  ******************************************************************************/
115*06803cfdSPritesh Raithatha const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = {
116*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
117*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, ENABLE),
118*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, ENABLE),
119*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE),
120*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE),
121*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
122*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
123*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
124*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
125*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE),
126*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
127*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(GPUSWR2, SECURE, NO_OVERRIDE, DISABLE),
128*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE),
129*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE),
130*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE),
131*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
132*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE),
133*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(SDMMCWAA, NON_SECURE, OVERRIDE, ENABLE),
134*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE),
135*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, ENABLE),
136*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, ENABLE),
137*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE),
138*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE),
139*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE),
140*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
141*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
142*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE),
143*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(ISPWA, NON_SECURE, OVERRIDE, ENABLE),
144*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE),
145*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE),
146*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
147*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(SDMMCRAA, NON_SECURE, OVERRIDE, ENABLE),
148*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(VIW, NON_SECURE, OVERRIDE, ENABLE),
149*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
150*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE),
151*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
152*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(ISPRA, NON_SECURE, OVERRIDE, ENABLE),
153*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
154*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE),
155*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
156*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, ENABLE),
157*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE),
158*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
159*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
160*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
161*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
162*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
163*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE),
164*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE),
165*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE),
166*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
167*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
168*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE),
169*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE),
170*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
171*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE),
172*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE),
173*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE),
174*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE),
175*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE),
176*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE),
177*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE),
178*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE),
179*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
180*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(GPUSWR, SECURE, NO_OVERRIDE, DISABLE),
181*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
182*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE),
183*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE),
184*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
185*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE),
186*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE),
187*06803cfdSPritesh Raithatha 	mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
188*06803cfdSPritesh Raithatha };
189*06803cfdSPritesh Raithatha 
190*06803cfdSPritesh Raithatha /*******************************************************************************
191*06803cfdSPritesh Raithatha  * Array to hold the transaction override configs
192*06803cfdSPritesh Raithatha  ******************************************************************************/
193*06803cfdSPritesh Raithatha const static mc_txn_override_cfg_t tegra186_txn_override_cfgs[] = {
194*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR),
195*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR),
196*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR),
197*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(SDMMCWAA, CGID_TAG_ADR),
198*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(MPCOREW, CGID_TAG_ADR),
199*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR),
200*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR),
201*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR),
202*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR),
203*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(GPUSWR, CGID_TAG_ADR),
204*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR),
205*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR),
206*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(GPUSWR2, CGID_TAG_ADR),
207*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR),
208*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(AONW, CGID_TAG_ADR),
209*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR),
210*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR),
211*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR),
212*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR),
213*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR),
214*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR),
215*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR),
216*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR),
217*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR),
218*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR),
219*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR),
220*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR),
221*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(APEW, CGID_TAG_ADR),
222*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR),
223*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(AFIW, CGID_TAG_ADR),
224*06803cfdSPritesh Raithatha 	mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR),
225*06803cfdSPritesh Raithatha };
226*06803cfdSPritesh Raithatha 
227*06803cfdSPritesh Raithatha /*******************************************************************************
228*06803cfdSPritesh Raithatha  * Struct to hold the memory controller settings
229*06803cfdSPritesh Raithatha  ******************************************************************************/
230*06803cfdSPritesh Raithatha static tegra_mc_settings_t tegra186_mc_settings = {
231*06803cfdSPritesh Raithatha 	.streamid_override_cfg = tegra186_streamid_override_regs,
232*06803cfdSPritesh Raithatha 	.num_streamid_override_cfgs = ARRAY_SIZE(tegra186_streamid_override_regs),
233*06803cfdSPritesh Raithatha 	.streamid_security_cfg = tegra186_streamid_sec_cfgs,
234*06803cfdSPritesh Raithatha 	.num_streamid_security_cfgs = ARRAY_SIZE(tegra186_streamid_sec_cfgs),
235*06803cfdSPritesh Raithatha 	.txn_override_cfg = tegra186_txn_override_cfgs,
236*06803cfdSPritesh Raithatha 	.num_txn_override_cfgs = ARRAY_SIZE(tegra186_txn_override_cfgs)
237*06803cfdSPritesh Raithatha };
238*06803cfdSPritesh Raithatha 
239*06803cfdSPritesh Raithatha /*******************************************************************************
240*06803cfdSPritesh Raithatha  * Handler to return the pointer to the memory controller's settings struct
241*06803cfdSPritesh Raithatha  ******************************************************************************/
242*06803cfdSPritesh Raithatha tegra_mc_settings_t *tegra_get_mc_settings(void)
243*06803cfdSPritesh Raithatha {
244*06803cfdSPritesh Raithatha 	return &tegra186_mc_settings;
245*06803cfdSPritesh Raithatha }
246