1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <errno.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <denver.h> 13 #include <lib/mmio.h> 14 15 #include <mce_private.h> 16 #include <t18x_ari.h> 17 #include <tegra_private.h> 18 19 int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) 20 { 21 int32_t ret = 0; 22 uint64_t val = 0ULL; 23 24 (void)ari_base; 25 26 /* check for allowed power state */ 27 if ((state != TEGRA_ARI_CORE_C0) && (state != TEGRA_ARI_CORE_C1) && 28 (state != TEGRA_ARI_CORE_C6) && (state != TEGRA_ARI_CORE_C7)) { 29 ERROR("%s: unknown cstate (%d)\n", __func__, state); 30 ret = EINVAL; 31 } else { 32 /* time (TSC ticks) until the core is expected to get a wake event */ 33 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, wake_time); 34 35 /* set the core cstate */ 36 val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK; 37 write_actlr_el1(val | (uint64_t)state); 38 } 39 40 return ret; 41 } 42 43 /* 44 * This request allows updating of CLUSTER_CSTATE, CCPLEX_CSTATE and 45 * SYSTEM_CSTATE values. 46 */ 47 int32_t nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, 48 uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, 49 uint8_t update_wake_mask) 50 { 51 uint64_t val = 0ULL; 52 53 (void)ari_base; 54 55 /* update CLUSTER_CSTATE? */ 56 if (cluster != 0U) { 57 val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) | 58 CLUSTER_CSTATE_UPDATE_BIT; 59 } 60 61 /* update CCPLEX_CSTATE? */ 62 if (ccplex != 0U) { 63 val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) | 64 CCPLEX_CSTATE_UPDATE_BIT; 65 } 66 67 /* update SYSTEM_CSTATE? */ 68 if (system != 0U) { 69 val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | 70 (((uint64_t)sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) | 71 SYSTEM_CSTATE_UPDATE_BIT); 72 } 73 74 /* update wake mask value? */ 75 if (update_wake_mask != 0U) { 76 val |= CSTATE_WAKE_MASK_UPDATE_BIT; 77 } 78 79 /* set the wake mask */ 80 val &= CSTATE_WAKE_MASK_CLEAR; 81 val |= ((uint64_t)wake_mask << CSTATE_WAKE_MASK_SHIFT); 82 83 /* set the updated cstate info */ 84 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val); 85 86 return 0; 87 } 88 89 int32_t nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time) 90 { 91 int32_t ret = 0; 92 93 (void)ari_base; 94 95 /* sanity check crossover type */ 96 if (type > TEGRA_ARI_CROSSOVER_CCP3_SC1) { 97 ret = EINVAL; 98 } else { 99 /* 100 * The crossover threshold limit types start from 101 * TEGRA_CROSSOVER_TYPE_C1_C6 to TEGRA_CROSSOVER_TYPE_CCP3_SC7. 102 * The command indices for updating the threshold be generated 103 * by adding the type to the NVG_SET_THRESHOLD_CROSSOVER_C1_C6 104 * command index. 105 */ 106 nvg_set_request_data((TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 + 107 (uint64_t)type), (uint64_t)time); 108 } 109 110 return ret; 111 } 112 113 uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state) 114 { 115 uint64_t ret; 116 117 (void)ari_base; 118 119 /* sanity check state */ 120 if (state == 0U) { 121 ret = EINVAL; 122 } else { 123 /* 124 * The cstate types start from NVG_READ_CSTATE_STATS_SC7_ENTRIES 125 * to NVG_GET_LAST_CSTATE_ENTRY_A57_3. The command indices for 126 * reading the threshold can be generated by adding the type to 127 * the NVG_CLEAR_CSTATE_STATS command index. 128 */ 129 nvg_set_request((TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR + 130 (uint64_t)state)); 131 ret = nvg_get_result(); 132 } 133 134 return ret; 135 } 136 137 int32_t nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) 138 { 139 uint64_t val; 140 141 (void)ari_base; 142 143 /* 144 * The only difference between a CSTATE_STATS_WRITE and 145 * CSTATE_STATS_READ is the usage of the 63:32 in the request. 146 * 63:32 are set to '0' for a read, while a write contains the 147 * actual stats value to be written. 148 */ 149 val = ((uint64_t)stats << MCE_CSTATE_STATS_TYPE_SHIFT) | state; 150 151 /* 152 * The cstate types start from NVG_READ_CSTATE_STATS_SC7_ENTRIES 153 * to NVG_GET_LAST_CSTATE_ENTRY_A57_3. The command indices for 154 * reading the threshold can be generated by adding the type to 155 * the NVG_CLEAR_CSTATE_STATS command index. 156 */ 157 nvg_set_request_data((TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR + 158 (uint64_t)state), val); 159 160 return 0; 161 } 162 163 int32_t nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) 164 { 165 (void)ari_base; 166 (void)state; 167 (void)wake_time; 168 169 /* This does not apply to the Denver cluster */ 170 return 0; 171 } 172 173 int32_t nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) 174 { 175 uint64_t val; 176 int32_t ret; 177 178 (void)ari_base; 179 180 /* check for allowed power state */ 181 if ((state != TEGRA_ARI_CORE_C0) && (state != TEGRA_ARI_CORE_C1) && 182 (state != TEGRA_ARI_CORE_C6) && (state != TEGRA_ARI_CORE_C7)) { 183 ERROR("%s: unknown cstate (%d)\n", __func__, state); 184 ret = EINVAL; 185 } else { 186 /* 187 * Request format - 188 * 63:32 = wake time 189 * 31:0 = C-state for this core 190 */ 191 val = ((uint64_t)wake_time << MCE_SC7_WAKE_TIME_SHIFT) | 192 ((uint64_t)state & MCE_SC7_ALLOWED_MASK); 193 194 /* issue command to check if SC7 is allowed */ 195 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED, val); 196 197 /* 1 = SC7 allowed, 0 = SC7 not allowed */ 198 ret = (nvg_get_result() != 0ULL) ? 1 : 0; 199 } 200 201 return ret; 202 } 203 204 int32_t nvg_online_core(uint32_t ari_base, uint32_t core) 205 { 206 uint64_t cpu = read_mpidr() & MPIDR_CPU_MASK; 207 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 208 int32_t ret = 0; 209 210 (void)ari_base; 211 212 /* sanity check code id */ 213 if ((core >= MCE_CORE_ID_MAX) || (cpu == core)) { 214 ERROR("%s: unsupported core id (%d)\n", __func__, core); 215 ret = EINVAL; 216 } else { 217 /* 218 * The Denver cluster has 2 CPUs only - 0, 1. 219 */ 220 if ((impl == DENVER_IMPL) && ((core == 2U) || (core == 3U))) { 221 ERROR("%s: unknown core id (%d)\n", __func__, core); 222 ret = EINVAL; 223 } else { 224 /* get a core online */ 225 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE, 226 ((uint64_t)core & MCE_CORE_ID_MASK)); 227 } 228 } 229 230 return ret; 231 } 232 233 int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable) 234 { 235 uint32_t val; 236 237 (void)ari_base; 238 239 /* 240 * If the enable bit is cleared, Auto-CC3 will be disabled by setting 241 * the SW visible voltage/frequency request registers for all non 242 * floorswept cores valid independent of StandbyWFI and disabling 243 * the IDLE voltage/frequency request register. If set, Auto-CC3 244 * will be enabled by setting the ARM SW visible voltage/frequency 245 * request registers for all non floorswept cores to be enabled by 246 * StandbyWFI or the equivalent signal, and always keeping the IDLE 247 * voltage/frequency request register enabled. 248 */ 249 val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\ 250 ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\ 251 ((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U)); 252 253 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CC3_CTRL, (uint64_t)val); 254 255 return 0; 256 } 257