1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef T18X_TEGRA_ARI_H 32 #define T18X_TEGRA_ARI_H 33 34 /* 35 * ---------------------------------------------------------------------------- 36 * t18x_ari.h 37 * 38 * Global ARI definitions. 39 * ---------------------------------------------------------------------------- 40 */ 41 42 enum { 43 TEGRA_ARI_VERSION_MAJOR = 3U, 44 TEGRA_ARI_VERSION_MINOR = 1U, 45 }; 46 47 typedef enum { 48 /* indexes below get the core lock */ 49 TEGRA_ARI_MISC = 0U, 50 /* index 1 is deprecated */ 51 /* index 2 is deprecated */ 52 /* index 3 is deprecated */ 53 TEGRA_ARI_ONLINE_CORE = 4U, 54 55 /* indexes below need cluster lock */ 56 TEGRA_ARI_MISC_CLUSTER = 41U, 57 TEGRA_ARI_IS_CCX_ALLOWED = 42U, 58 TEGRA_ARI_CC3_CTRL = 43U, 59 60 /* indexes below need ccplex lock */ 61 TEGRA_ARI_ENTER_CSTATE = 80U, 62 TEGRA_ARI_UPDATE_CSTATE_INFO = 81U, 63 TEGRA_ARI_IS_SC7_ALLOWED = 82U, 64 /* index 83 is deprecated */ 65 TEGRA_ARI_PERFMON = 84U, 66 TEGRA_ARI_UPDATE_CCPLEX_GSC = 85U, 67 /* index 86 is depracated */ 68 /* index 87 is deprecated */ 69 TEGRA_ARI_ROC_FLUSH_CACHE_ONLY = 88U, 70 TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS = 89U, 71 TEGRA_ARI_MISC_CCPLEX = 90U, 72 TEGRA_ARI_MCA = 91U, 73 TEGRA_ARI_UPDATE_CROSSOVER = 92U, 74 TEGRA_ARI_CSTATE_STATS = 93U, 75 TEGRA_ARI_WRITE_CSTATE_STATS = 94U, 76 TEGRA_ARI_COPY_MISCREG_AA64_RST = 95U, 77 TEGRA_ARI_ROC_CLEAN_CACHE_ONLY = 96U, 78 } tegra_ari_req_id_t; 79 80 typedef enum { 81 TEGRA_ARI_MISC_ECHO = 0U, 82 TEGRA_ARI_MISC_VERSION = 1U, 83 TEGRA_ARI_MISC_FEATURE_LEAF_0 = 2U, 84 } tegra_ari_misc_index_t; 85 86 typedef enum { 87 TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF = 0U, 88 TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT = 1U, 89 TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL = 2U, 90 TEGRA_ARI_MISC_CCPLEX_EDBGREQ = 3U, 91 } tegra_ari_misc_ccplex_index_t; 92 93 typedef enum { 94 TEGRA_ARI_CORE_C0 = 0U, 95 TEGRA_ARI_CORE_C1 = 1U, 96 TEGRA_ARI_CORE_C6 = 6U, 97 TEGRA_ARI_CORE_C7 = 7U, 98 TEGRA_ARI_CORE_WARMRSTREQ = 8U, 99 } tegra_ari_core_sleep_state_t; 100 101 typedef enum { 102 TEGRA_ARI_CLUSTER_CC0 = 0U, 103 TEGRA_ARI_CLUSTER_CC1 = 1U, 104 TEGRA_ARI_CLUSTER_CC6 = 6U, 105 TEGRA_ARI_CLUSTER_CC7 = 7U, 106 } tegra_ari_cluster_sleep_state_t; 107 108 typedef enum { 109 TEGRA_ARI_CCPLEX_CCP0 = 0U, 110 TEGRA_ARI_CCPLEX_CCP1 = 1U, 111 TEGRA_ARI_CCPLEX_CCP3 = 3U, /* obsoleted */ 112 } tegra_ari_ccplex_sleep_state_t; 113 114 typedef enum { 115 TEGRA_ARI_SYSTEM_SC0 = 0U, 116 TEGRA_ARI_SYSTEM_SC1 = 1U, /* obsoleted */ 117 TEGRA_ARI_SYSTEM_SC2 = 2U, /* obsoleted */ 118 TEGRA_ARI_SYSTEM_SC3 = 3U, /* obsoleted */ 119 TEGRA_ARI_SYSTEM_SC4 = 4U, /* obsoleted */ 120 TEGRA_ARI_SYSTEM_SC7 = 7U, 121 TEGRA_ARI_SYSTEM_SC8 = 8U, 122 } tegra_ari_system_sleep_state_t; 123 124 typedef enum { 125 TEGRA_ARI_CROSSOVER_C1_C6 = 0U, 126 TEGRA_ARI_CROSSOVER_CC1_CC6 = 1U, 127 TEGRA_ARI_CROSSOVER_CC1_CC7 = 2U, 128 TEGRA_ARI_CROSSOVER_CCP1_CCP3 = 3U, /* obsoleted */ 129 TEGRA_ARI_CROSSOVER_CCP3_SC2 = 4U, /* obsoleted */ 130 TEGRA_ARI_CROSSOVER_CCP3_SC3 = 5U, /* obsoleted */ 131 TEGRA_ARI_CROSSOVER_CCP3_SC4 = 6U, /* obsoleted */ 132 TEGRA_ARI_CROSSOVER_CCP3_SC7 = 7U, /* obsoleted */ 133 TEGRA_ARI_CROSSOVER_SC0_SC7 = 7U, 134 TEGRA_ARI_CROSSOVER_CCP3_SC1 = 8U, /* obsoleted */ 135 } tegra_ari_crossover_index_t; 136 137 typedef enum { 138 TEGRA_ARI_CSTATE_STATS_CLEAR = 0U, 139 TEGRA_ARI_CSTATE_STATS_SC7_ENTRIES = 1U, 140 TEGRA_ARI_CSTATE_STATS_SC4_ENTRIES, /* obsoleted */ 141 TEGRA_ARI_CSTATE_STATS_SC3_ENTRIES, /* obsoleted */ 142 TEGRA_ARI_CSTATE_STATS_SC2_ENTRIES, /* obsoleted */ 143 TEGRA_ARI_CSTATE_STATS_CCP3_ENTRIES, /* obsoleted */ 144 TEGRA_ARI_CSTATE_STATS_A57_CC6_ENTRIES, 145 TEGRA_ARI_CSTATE_STATS_A57_CC7_ENTRIES, 146 TEGRA_ARI_CSTATE_STATS_D15_CC6_ENTRIES, 147 TEGRA_ARI_CSTATE_STATS_D15_CC7_ENTRIES, 148 TEGRA_ARI_CSTATE_STATS_D15_0_C6_ENTRIES, 149 TEGRA_ARI_CSTATE_STATS_D15_1_C6_ENTRIES, 150 TEGRA_ARI_CSTATE_STATS_D15_0_C7_ENTRIES = 14U, 151 TEGRA_ARI_CSTATE_STATS_D15_1_C7_ENTRIES, 152 TEGRA_ARI_CSTATE_STATS_A57_0_C7_ENTRIES = 18U, 153 TEGRA_ARI_CSTATE_STATS_A57_1_C7_ENTRIES, 154 TEGRA_ARI_CSTATE_STATS_A57_2_C7_ENTRIES, 155 TEGRA_ARI_CSTATE_STATS_A57_3_C7_ENTRIES, 156 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_0, 157 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_1, 158 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 26U, 159 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_1, 160 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_2, 161 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_3, 162 } tegra_ari_cstate_stats_index_t; 163 164 typedef enum { 165 TEGRA_ARI_GSC_ALL = 0U, 166 TEGRA_ARI_GSC_BPMP = 6U, 167 TEGRA_ARI_GSC_APE = 7U, 168 TEGRA_ARI_GSC_SPE = 8U, 169 TEGRA_ARI_GSC_SCE = 9U, 170 TEGRA_ARI_GSC_APR = 10U, 171 TEGRA_ARI_GSC_TZRAM = 11U, 172 TEGRA_ARI_GSC_SE = 12U, 173 TEGRA_ARI_GSC_BPMP_TO_SPE = 16U, 174 TEGRA_ARI_GSC_SPE_TO_BPMP = 17U, 175 TEGRA_ARI_GSC_CPU_TZ_TO_BPMP = 18U, 176 TEGRA_ARI_GSC_BPMP_TO_CPU_TZ = 19U, 177 TEGRA_ARI_GSC_CPU_NS_TO_BPMP = 20U, 178 TEGRA_ARI_GSC_BPMP_TO_CPU_NS = 21U, 179 TEGRA_ARI_GSC_IPC_SE_SPE_SCE_BPMP = 22U, 180 TEGRA_ARI_GSC_SC7_RESUME_FW = 23U, 181 TEGRA_ARI_GSC_TZ_DRAM_IDX = 34U, 182 TEGRA_ARI_GSC_VPR_IDX = 35U, 183 } tegra_ari_gsc_index_t; 184 185 /* This macro will produce enums for __name##_LSB, __name##_MSB and __name##_MSK */ 186 #define TEGRA_ARI_ENUM_MASK_LSB_MSB(__name, __lsb, __msb) __name##_LSB = __lsb, __name##_MSB = __msb 187 188 typedef enum { 189 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CLUSTER_CSTATE, 0U, 2U), 190 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CLUSTER_CSTATE_PRESENT, 7U, 7U), 191 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CCPLEX_CSTATE, 8U, 9U), 192 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CCPLEX_CSTATE_PRESENT, 15U, 15U), 193 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__SYSTEM_CSTATE, 16U, 19U), 194 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__IGNORE_CROSSOVERS, 22U, 22U), 195 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__SYSTEM_CSTATE_PRESENT, 23U, 23U), 196 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__WAKE_MASK_PRESENT, 31U, 31U), 197 } tegra_ari_update_cstate_info_bitmasks_t; 198 199 typedef enum { 200 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL__EN, 0U, 0U), 201 } tegra_ari_misc_ccplex_bitmasks_t; 202 203 typedef enum { 204 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__IDLE_FREQ, 0U, 8U), 205 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__IDLE_VOLT, 16U, 23U), 206 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__ENABLE, 31U, 31U), 207 } tegra_ari_cc3_ctrl_bitmasks_t; 208 209 typedef enum { 210 TEGRA_ARI_MCA_NOP = 0U, 211 TEGRA_ARI_MCA_READ_SERR = 1U, 212 TEGRA_ARI_MCA_WRITE_SERR = 2U, 213 TEGRA_ARI_MCA_CLEAR_SERR = 4U, 214 TEGRA_ARI_MCA_REPORT_SERR = 5U, 215 TEGRA_ARI_MCA_READ_INTSTS = 6U, 216 TEGRA_ARI_MCA_WRITE_INTSTS = 7U, 217 TEGRA_ARI_MCA_READ_PREBOOT_SERR = 8U, 218 } tegra_ari_mca_commands_t; 219 220 typedef enum { 221 TEGRA_ARI_MCA_RD_WR_DPMU = 0U, 222 TEGRA_ARI_MCA_RD_WR_IOB = 1U, 223 TEGRA_ARI_MCA_RD_WR_MCB = 2U, 224 TEGRA_ARI_MCA_RD_WR_CCE = 3U, 225 TEGRA_ARI_MCA_RD_WR_CQX = 4U, 226 TEGRA_ARI_MCA_RD_WR_CTU = 5U, 227 TEGRA_ARI_MCA_RD_WR_JSR_MTS = 7U, 228 TEGRA_ARI_MCA_RD_BANK_INFO = 0x0fU, 229 TEGRA_ARI_MCA_RD_BANK_TEMPLATE = 0x10U, 230 TEGRA_ARI_MCA_RD_WR_SECURE_ACCESS_REGISTER = 0x11U, 231 TEGRA_ARI_MCA_RD_WR_GLOBAL_CONFIG_REGISTER = 0x12U, 232 } tegra_ari_mca_rd_wr_indexes_t; 233 234 typedef enum { 235 TEGRA_ARI_MCA_RD_WR_ASERRX_CTRL = 0U, 236 TEGRA_ARI_MCA_RD_WR_ASERRX_STATUS = 1U, 237 TEGRA_ARI_MCA_RD_WR_ASERRX_ADDR = 2U, 238 TEGRA_ARI_MCA_RD_WR_ASERRX_MISC1 = 3U, 239 TEGRA_ARI_MCA_RD_WR_ASERRX_MISC2 = 4U, 240 } tegra_ari_mca_read_asserx_subindexes_t; 241 242 typedef enum { 243 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_SETTING_ENABLES_NS_PERMITTED, 0U, 0U), 244 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_READING_STATUS_NS_PERMITTED, 1U, 1U), 245 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_PENDING_MCA_ERRORS_NS_PERMITTED, 2U, 2U), 246 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_CLEARING_MCA_INTERRUPTS_NS_PERMITTED, 3U, 3U), 247 } tegra_ari_mca_secure_register_bitmasks_t; 248 249 typedef enum { 250 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_SERR_ERR_CODE, 0U, 15U), 251 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_PWM_ERR, 16U, 16U), 252 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_CRAB_ERR, 17U, 17U), 253 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_RD_WR_N, 18U, 18U), 254 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_UCODE_ERR, 19U, 19U), 255 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_PWM, 20U, 23U), 256 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_AV, 58U, 58U), 257 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_MV, 59U, 59U), 258 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_EN, 60U, 60U), 259 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_UC, 61U, 61U), 260 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_OVF, 62U, 62U), 261 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_VAL, 63U, 63U), 262 263 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_ADDR_ADDR, 0U, 41U), 264 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_ADDR_UCODE_ERRCD, 42U, 52U), 265 266 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_PWM_ERR, 0U, 0U), 267 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_CRAB_ERR, 1U, 1U), 268 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_UCODE_ERR, 3U, 3U), 269 } tegra_ari_mca_aserr0_bitmasks_t; 270 271 typedef enum { 272 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_SERR_ERR_CODE, 0U, 15U), 273 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MSI_ERR, 16U, 16U), 274 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_IHI_ERR, 17U, 17U), 275 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CRI_ERR, 18U, 18U), 276 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MMCRAB_ERR, 19U, 19U), 277 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CSI_ERR, 20U, 20U), 278 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_RD_WR_N, 21U, 21U), 279 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_REQ_ERRT, 22U, 23U), 280 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_RESP_ERRT, 24U, 25U), 281 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_AV, 58U, 58U), 282 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MV, 59U, 59U), 283 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_EN, 60U, 60U), 284 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_UC, 61U, 61U), 285 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_OVF, 62U, 62U), 286 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_VAL, 63U, 63U), 287 288 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_AXI_ID, 0U, 7U), 289 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_ID, 8U, 27U), 290 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_CID, 28U, 31U), 291 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_CMD, 32U, 35U), 292 293 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_MSI_ERR, 0U, 0U), 294 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_IHI_ERR, 1U, 1U), 295 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_CRI_ERR, 2U, 2U), 296 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_MMCRAB_ERR, 3U, 3U), 297 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_CSI_ERR, 4U, 4U), 298 299 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_MISC_ADDR, 0U, 41U), 300 } tegra_ari_mca_aserr1_bitmasks_t; 301 302 typedef enum { 303 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_SERR_ERR_CODE, 0U, 15U), 304 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_MC_ERR, 16U, 16U), 305 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_SYSRAM_ERR, 17U, 17U), 306 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_CLIENT_ID, 18U, 19U), 307 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_AV, 58U, 58U), 308 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_MV, 59U, 59U), 309 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_EN, 60U, 60U), 310 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_UC, 61U, 61U), 311 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_OVF, 62U, 62U), 312 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_VAL, 63U, 63U), 313 314 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_ID, 0U, 17U), 315 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_CMD, 18U, 21U), 316 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_ADDR, 22U, 53U), 317 318 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_CTRL_EN_MC_ERR, 0U, 0U), 319 } tegra_ari_mca_aserr2_bitmasks_t; 320 321 typedef enum { 322 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_SERR_ERR_CODE, 0U, 15U), 323 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_TO_ERR, 16U, 16U), 324 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_STAT_ERR, 17U, 17U), 325 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_DST_ERR, 18U, 18U), 326 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_UNC_ERR, 19U, 19U), 327 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_MH_ERR, 20U, 20U), 328 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_PERR, 21U, 21U), 329 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_PSN_ERR, 22U, 22U), 330 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_AV, 58U, 58U), 331 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_MV, 59U, 59U), 332 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_EN, 60U, 60U), 333 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_UC, 61U, 61U), 334 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_OVF, 62U, 62U), 335 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_VAL, 63U, 63U), 336 337 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_ADDR_CMD, 0U, 5U), 338 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_ADDR_ADDR, 6U, 47U), 339 340 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_TO, 0U, 0U), 341 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_DIV4, 1U, 1U), 342 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_TLIMIT, 2U, 11U), 343 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_PSN_ERR_CORR_MSK, 12U, 25U), 344 345 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_MORE_INFO, 0U, 17U), 346 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_TO_INFO, 18U, 43U), 347 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_SRC, 44U, 45U), 348 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_TID, 46U, 52U), 349 350 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_TO_ERR, 0U, 0U), 351 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_STAT_ERR, 1U, 1U), 352 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_DST_ERR, 2U, 2U), 353 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_UNC_ERR, 3U, 3U), 354 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_MH_ERR, 4U, 4U), 355 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_PERR, 5U, 5U), 356 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_PSN_ERR, 6U, 19U), 357 } tegra_ari_mca_aserr3_bitmasks_t; 358 359 typedef enum { 360 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_SERR_ERR_CODE, 0U, 15U), 361 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_SRC_ERR, 16U, 16U), 362 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_DST_ERR, 17U, 17U), 363 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_REQ_ERR, 18U, 18U), 364 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_RSP_ERR, 19U, 19U), 365 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_AV, 58U, 58U), 366 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_MV, 59U, 59U), 367 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_EN, 60U, 60U), 368 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_UC, 61U, 61U), 369 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_OVF, 62U, 62U), 370 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_VAL, 63U, 63U), 371 372 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_CTRL_EN_CPE_ERR, 0U, 0U), 373 } tegra_ari_mca_aserr4_bitmasks_t; 374 375 typedef enum { 376 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_SERR_ERR_CODE, 0U, 15U), 377 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_CTUPAR, 16U, 16U), 378 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_MULTI, 17U, 17U), 379 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_AV, 58U, 58U), 380 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_MV, 59U, 59U), 381 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_EN, 60U, 60U), 382 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_UC, 61U, 61U), 383 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_OVF, 62U, 62U), 384 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_VAL, 63U, 63U), 385 386 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_SRC, 0U, 7U), 387 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_ID, 8U, 15U), 388 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_DATA, 16U, 26U), 389 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_CMD, 32U, 35U), 390 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_ADDR, 36U, 45U), 391 392 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_CTRL_EN_CTUPAR, 0U, 0U), 393 } tegra_ari_mca_aserr5_bitmasks_t; 394 395 typedef enum { 396 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_SERR_ERR_CODE, 0U, 15U), 397 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_AV, 58U, 58U), 398 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_MV, 59U, 59U), 399 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_EN, 60U, 60U), 400 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_UC, 61U, 61U), 401 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_OVF, 62U, 62U), 402 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_VAL, 63U, 63U), 403 404 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_ADDR_TBD_INFO, 0U, 63U), 405 } tegra_ari_mca_serr1_bitmasks_t; 406 407 #undef TEGRA_ARI_ENUM_MASK_LSB_MSB 408 409 typedef enum { 410 TEGRA_NVG_CHANNEL_PMIC = 0U, 411 TEGRA_NVG_CHANNEL_POWER_PERF = 1U, 412 TEGRA_NVG_CHANNEL_POWER_MODES = 2U, 413 TEGRA_NVG_CHANNEL_WAKE_TIME = 3U, 414 TEGRA_NVG_CHANNEL_CSTATE_INFO = 4U, 415 TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 = 5U, 416 TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC6 = 6U, 417 TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC7 = 7U, 418 TEGRA_NVG_CHANNEL_CROSSOVER_CCP1_CCP3 = 8U, /* obsoleted */ 419 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC2 = 9U, /* obsoleted */ 420 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC3 = 10U, /* obsoleted */ 421 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC4 = 11U, /* obsoleted */ 422 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC7 = 12U, /* obsoleted */ 423 TEGRA_NVG_CHANNEL_CROSSOVER_SC0_SC7 = 12U, 424 TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR = 13U, 425 TEGRA_NVG_CHANNEL_CSTATE_STATS_SC7_ENTRIES = 14U, 426 TEGRA_NVG_CHANNEL_CSTATE_STATS_SC4_ENTRIES = 15U, /* obsoleted */ 427 TEGRA_NVG_CHANNEL_CSTATE_STATS_SC3_ENTRIES = 16U, /* obsoleted */ 428 TEGRA_NVG_CHANNEL_CSTATE_STATS_SC2_ENTRIES = 17U, /* obsoleted */ 429 TEGRA_NVG_CHANNEL_CSTATE_STATS_CCP3_ENTRIES = 18U, /* obsoleted */ 430 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC6_ENTRIES = 19U, 431 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC7_ENTRIES = 20U, 432 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC6_ENTRIES = 21U, 433 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC7_ENTRIES = 22U, 434 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_0_C6_ENTRIES = 23U, 435 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_1_C6_ENTRIES = 24U, 436 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_2_C6_ENTRIES = 25U, /* Reserved (for Denver15 core 2) */ 437 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_3_C6_ENTRIES = 26U, /* Reserved (for Denver15 core 3) */ 438 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_0_C7_ENTRIES = 27U, 439 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_1_C7_ENTRIES = 28U, 440 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_2_C7_ENTRIES = 29U, /* Reserved (for Denver15 core 2) */ 441 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_3_C7_ENTRIES = 30U, /* Reserved (for Denver15 core 3) */ 442 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_0_C7_ENTRIES = 31U, 443 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_1_C7_ENTRIES = 32U, 444 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_2_C7_ENTRIES = 33U, 445 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_3_C7_ENTRIES = 34U, 446 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_0 = 35U, 447 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_1 = 36U, 448 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_2 = 37U, /* Reserved (for Denver15 core 2) */ 449 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_3 = 38U, /* Reserved (for Denver15 core 3) */ 450 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 39U, 451 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_1 = 40U, 452 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_2 = 41U, 453 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_3 = 42U, 454 TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43U, 455 TEGRA_NVG_CHANNEL_ONLINE_CORE = 44U, 456 TEGRA_NVG_CHANNEL_CC3_CTRL = 45U, 457 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC1 = 46U, /* obsoleted */ 458 TEGRA_NVG_CHANNEL_LAST_INDEX, 459 } tegra_nvg_channel_id_t; 460 461 #endif /* T18X_TEGRA_ARI_H */ 462