1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef T18X_TEGRA_ARI_H 32 #define T18X_TEGRA_ARI_H 33 34 /* 35 * ---------------------------------------------------------------------------- 36 * t18x_ari.h 37 * 38 * Global ARI definitions. 39 * ---------------------------------------------------------------------------- 40 */ 41 42 enum { 43 TEGRA_ARI_VERSION_MAJOR = 2, 44 TEGRA_ARI_VERSION_MINOR = 19, 45 }; 46 47 typedef enum { 48 /* indexes below get the core lock */ 49 TEGRA_ARI_MISC = 0, 50 /* index 1 is deprecated */ 51 /* index 2 is deprecated */ 52 /* index 3 is deprecated */ 53 TEGRA_ARI_ONLINE_CORE = 4, 54 55 /* indexes below need cluster lock */ 56 TEGRA_ARI_MISC_CLUSTER = 41, 57 TEGRA_ARI_IS_CCX_ALLOWED = 42, 58 TEGRA_ARI_CC3_CTRL = 43, 59 60 /* indexes below need ccplex lock */ 61 TEGRA_ARI_ENTER_CSTATE = 80, 62 TEGRA_ARI_UPDATE_CSTATE_INFO = 81, 63 TEGRA_ARI_IS_SC7_ALLOWED = 82, 64 /* index 83 is deprecated */ 65 TEGRA_ARI_PERFMON = 84, 66 TEGRA_ARI_UPDATE_CCPLEX_GSC = 85, 67 /* index 86 is depracated */ 68 /* index 87 is deprecated */ 69 TEGRA_ARI_ROC_FLUSH_CACHE_ONLY = 88, 70 TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS = 89, 71 TEGRA_ARI_MISC_CCPLEX = 90, 72 TEGRA_ARI_MCA = 91, 73 TEGRA_ARI_UPDATE_CROSSOVER = 92, 74 TEGRA_ARI_CSTATE_STATS = 93, 75 TEGRA_ARI_WRITE_CSTATE_STATS = 94, 76 TEGRA_ARI_COPY_MISCREG_AA64_RST = 95, 77 TEGRA_ARI_ROC_CLEAN_CACHE_ONLY = 96, 78 } tegra_ari_req_id_t; 79 80 typedef enum { 81 TEGRA_ARI_MISC_ECHO = 0, 82 TEGRA_ARI_MISC_VERSION = 1, 83 TEGRA_ARI_MISC_FEATURE_LEAF_0 = 2, 84 } tegra_ari_misc_index_t; 85 86 typedef enum { 87 TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF = 0, 88 TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT = 1, 89 TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL = 2, 90 } tegra_ari_misc_ccplex_index_t; 91 92 typedef enum { 93 TEGRA_ARI_CORE_C0 = 0, 94 TEGRA_ARI_CORE_C1 = 1, 95 TEGRA_ARI_CORE_C6 = 6, 96 TEGRA_ARI_CORE_C7 = 7, 97 TEGRA_ARI_CORE_WARMRSTREQ = 8, 98 } tegra_ari_core_sleep_state_t; 99 100 typedef enum { 101 TEGRA_ARI_CLUSTER_CC0 = 0, 102 TEGRA_ARI_CLUSTER_CC1 = 1, 103 TEGRA_ARI_CLUSTER_CC6 = 6, 104 TEGRA_ARI_CLUSTER_CC7 = 7, 105 } tegra_ari_cluster_sleep_state_t; 106 107 typedef enum { 108 TEGRA_ARI_CCPLEX_CCP0 = 0, 109 TEGRA_ARI_CCPLEX_CCP1 = 1, 110 TEGRA_ARI_CCPLEX_CCP3 = 3, 111 } tegra_ari_ccplex_sleep_state_t; 112 113 typedef enum { 114 TEGRA_ARI_SYSTEM_SC0 = 0, 115 TEGRA_ARI_SYSTEM_SC1 = 1, 116 TEGRA_ARI_SYSTEM_SC2 = 2, 117 TEGRA_ARI_SYSTEM_SC3 = 3, 118 TEGRA_ARI_SYSTEM_SC4 = 4, 119 TEGRA_ARI_SYSTEM_SC7 = 7, 120 TEGRA_ARI_SYSTEM_SC8 = 8, 121 } tegra_ari_system_sleep_state_t; 122 123 typedef enum { 124 TEGRA_ARI_CROSSOVER_C1_C6 = 0, 125 TEGRA_ARI_CROSSOVER_CC1_CC6 = 1, 126 TEGRA_ARI_CROSSOVER_CC1_CC7 = 2, 127 TEGRA_ARI_CROSSOVER_CCP1_CCP3 = 3, 128 TEGRA_ARI_CROSSOVER_CCP3_SC2 = 4, 129 TEGRA_ARI_CROSSOVER_CCP3_SC3 = 5, 130 TEGRA_ARI_CROSSOVER_CCP3_SC4 = 6, 131 TEGRA_ARI_CROSSOVER_CCP3_SC7 = 7, 132 TEGRA_ARI_CROSSOVER_CCP3_SC1 = 8, 133 } tegra_ari_crossover_index_t; 134 135 typedef enum { 136 TEGRA_ARI_CSTATE_STATS_CLEAR = 0, 137 TEGRA_ARI_CSTATE_STATS_SC7_ENTRIES = 1, 138 TEGRA_ARI_CSTATE_STATS_SC4_ENTRIES, 139 TEGRA_ARI_CSTATE_STATS_SC3_ENTRIES, 140 TEGRA_ARI_CSTATE_STATS_SC2_ENTRIES, 141 TEGRA_ARI_CSTATE_STATS_CCP3_ENTRIES, 142 TEGRA_ARI_CSTATE_STATS_A57_CC6_ENTRIES, 143 TEGRA_ARI_CSTATE_STATS_A57_CC7_ENTRIES, 144 TEGRA_ARI_CSTATE_STATS_D15_CC6_ENTRIES, 145 TEGRA_ARI_CSTATE_STATS_D15_CC7_ENTRIES, 146 TEGRA_ARI_CSTATE_STATS_D15_0_C6_ENTRIES, 147 TEGRA_ARI_CSTATE_STATS_D15_1_C6_ENTRIES, 148 TEGRA_ARI_CSTATE_STATS_D15_0_C7_ENTRIES = 14, 149 TEGRA_ARI_CSTATE_STATS_D15_1_C7_ENTRIES, 150 TEGRA_ARI_CSTATE_STATS_A57_0_C7_ENTRIES = 18, 151 TEGRA_ARI_CSTATE_STATS_A57_1_C7_ENTRIES, 152 TEGRA_ARI_CSTATE_STATS_A57_2_C7_ENTRIES, 153 TEGRA_ARI_CSTATE_STATS_A57_3_C7_ENTRIES, 154 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_0, 155 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_1, 156 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 26, 157 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_1, 158 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_2, 159 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_3, 160 } tegra_ari_cstate_stats_index_t; 161 162 typedef enum { 163 TEGRA_ARI_GSC_ALL = 0, 164 165 TEGRA_ARI_GSC_BPMP = 6, 166 TEGRA_ARI_GSC_APE = 7, 167 TEGRA_ARI_GSC_SPE = 8, 168 TEGRA_ARI_GSC_SCE = 9, 169 TEGRA_ARI_GSC_APR = 10, 170 TEGRA_ARI_GSC_TZRAM = 11, 171 TEGRA_ARI_GSC_SE = 12, 172 173 TEGRA_ARI_GSC_BPMP_TO_SPE = 16, 174 TEGRA_ARI_GSC_SPE_TO_BPMP = 17, 175 TEGRA_ARI_GSC_CPU_TZ_TO_BPMP = 18, 176 TEGRA_ARI_GSC_BPMP_TO_CPU_TZ = 19, 177 TEGRA_ARI_GSC_CPU_NS_TO_BPMP = 20, 178 TEGRA_ARI_GSC_BPMP_TO_CPU_NS = 21, 179 TEGRA_ARI_GSC_IPC_SE_SPE_SCE_BPMP = 22, 180 TEGRA_ARI_GSC_SC7_RESUME_FW = 23, 181 182 TEGRA_ARI_GSC_TZ_DRAM_IDX = 34, 183 TEGRA_ARI_GSC_VPR_IDX = 35, 184 } tegra_ari_gsc_index_t; 185 186 /* This macro will produce enums for __name##_LSB, __name##_MSB and __name##_MSK */ 187 #define TEGRA_ARI_ENUM_MASK_LSB_MSB(__name, __lsb, __msb) __name##_LSB = __lsb, __name##_MSB = __msb 188 189 typedef enum { 190 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CLUSTER_CSTATE, 0, 2), 191 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CLUSTER_CSTATE_PRESENT, 7, 7), 192 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CCPLEX_CSTATE, 8, 9), 193 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CCPLEX_CSTATE_PRESENT, 15, 15), 194 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__SYSTEM_CSTATE, 16, 19), 195 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__IGNORE_CROSSOVERS, 22, 22), 196 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__SYSTEM_CSTATE_PRESENT, 23, 23), 197 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__WAKE_MASK_PRESENT, 31, 31), 198 } tegra_ari_update_cstate_info_bitmasks_t; 199 200 typedef enum { 201 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL__EN, 0, 0), 202 } tegra_ari_misc_ccplex_bitmasks_t; 203 204 typedef enum { 205 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__IDLE_FREQ, 0, 8), 206 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__IDLE_VOLT, 16, 23), 207 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__ENABLE, 31, 31), 208 } tegra_ari_cc3_ctrl_bitmasks_t; 209 210 typedef enum { 211 TEGRA_ARI_MCA_NOP = 0, 212 TEGRA_ARI_MCA_READ_SERR = 1, 213 TEGRA_ARI_MCA_WRITE_SERR = 2, 214 TEGRA_ARI_MCA_CLEAR_SERR = 4, 215 TEGRA_ARI_MCA_REPORT_SERR = 5, 216 TEGRA_ARI_MCA_READ_INTSTS = 6, 217 TEGRA_ARI_MCA_WRITE_INTSTS = 7, 218 TEGRA_ARI_MCA_READ_PREBOOT_SERR = 8, 219 } tegra_ari_mca_commands_t; 220 221 typedef enum { 222 TEGRA_ARI_MCA_RD_WR_DPMU = 0, 223 TEGRA_ARI_MCA_RD_WR_IOB = 1, 224 TEGRA_ARI_MCA_RD_WR_MCB = 2, 225 TEGRA_ARI_MCA_RD_WR_CCE = 3, 226 TEGRA_ARI_MCA_RD_WR_CQX = 4, 227 TEGRA_ARI_MCA_RD_WR_CTU = 5, 228 TEGRA_ARI_MCA_RD_BANK_INFO = 0x0f, 229 TEGRA_ARI_MCA_RD_BANK_TEMPLATE = 0x10, 230 TEGRA_ARI_MCA_RD_WR_SECURE_ACCESS_REGISTER = 0x11, 231 TEGRA_ARI_MCA_RD_WR_GLOBAL_CONFIG_REGISTER = 0x12, 232 } tegra_ari_mca_rd_wr_indexes_t; 233 234 typedef enum { 235 TEGRA_ARI_MCA_RD_WR_ASERRX_CTRL = 0, 236 TEGRA_ARI_MCA_RD_WR_ASERRX_STATUS = 1, 237 TEGRA_ARI_MCA_RD_WR_ASERRX_ADDR = 2, 238 TEGRA_ARI_MCA_RD_WR_ASERRX_MISC1 = 3, 239 TEGRA_ARI_MCA_RD_WR_ASERRX_MISC2 = 4, 240 } tegra_ari_mca_read_asserx_subindexes_t; 241 242 typedef enum { 243 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_SETTING_ENABLES_NS_PERMITTED, 0, 0), 244 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_READING_STATUS_NS_PERMITTED, 1, 1), 245 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_PENDING_MCA_ERRORS_NS_PERMITTED, 2, 2), 246 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_CLEARING_MCA_INTERRUPTS_NS_PERMITTED, 3, 3), 247 } tegra_ari_mca_secure_register_bitmasks_t; 248 249 typedef enum { 250 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_SERR_ERR_CODE, 0, 15), 251 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_PWM_ERR, 16, 16), 252 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_CRAB_ERR, 17, 17), 253 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_RD_WR_N, 18, 18), 254 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_UCODE_ERR, 19, 19), 255 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_PWM, 20, 23), 256 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_AV, 58, 58), 257 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_MV, 59, 59), 258 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_EN, 60, 60), 259 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_UC, 61, 61), 260 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_OVF, 62, 62), 261 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_VAL, 63, 63), 262 263 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_ADDR_ADDR, 0, 41), 264 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_ADDR_UCODE_ERRCD, 42, 52), 265 266 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_PWM_ERR, 0, 0), 267 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_CRAB_ERR, 1, 1), 268 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_UCODE_ERR, 3, 3), 269 } tegra_ari_mca_aserr0_bitmasks_t; 270 271 typedef enum { 272 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_SERR_ERR_CODE, 0, 15), 273 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MSI_ERR, 16, 16), 274 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_IHI_ERR, 17, 17), 275 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CRI_ERR, 18, 18), 276 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MMCRAB_ERR, 19, 19), 277 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CSI_ERR, 20, 20), 278 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_RD_WR_N, 21, 21), 279 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_REQ_ERRT, 22, 23), 280 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_RESP_ERRT, 24, 25), 281 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_AV, 58, 58), 282 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MV, 59, 59), 283 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_EN, 60, 60), 284 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_UC, 61, 61), 285 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_OVF, 62, 62), 286 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_VAL, 63, 63), 287 288 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_AXI_ID, 0, 7), 289 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_ID, 8, 27), 290 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_CID, 28, 31), 291 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_CMD, 32, 35), 292 293 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_MSI_ERR, 0, 0), 294 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_IHI_ERR, 1, 1), 295 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_CRI_ERR, 2, 2), 296 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_MMCRAB_ERR, 3, 3), 297 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_CSI_ERR, 4, 4), 298 299 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_MISC_ADDR, 0, 41), 300 } tegra_ari_mca_aserr1_bitmasks_t; 301 302 typedef enum { 303 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_SERR_ERR_CODE, 0, 15), 304 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_MC_ERR, 16, 16), 305 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_SYSRAM_ERR, 17, 17), 306 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_CLIENT_ID, 18, 19), 307 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_AV, 58, 58), 308 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_MV, 59, 59), 309 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_EN, 60, 60), 310 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_UC, 61, 61), 311 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_OVF, 62, 62), 312 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_VAL, 63, 63), 313 314 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_ID, 0, 17), 315 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_CMD, 18, 21), 316 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_ADDR, 22, 53), 317 318 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_CTRL_EN_MC_ERR, 0, 0), 319 } tegra_ari_mca_aserr2_bitmasks_t; 320 321 typedef enum { 322 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_SERR_ERR_CODE, 0, 15), 323 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_TO_ERR, 16, 16), 324 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_STAT_ERR, 17, 17), 325 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_DST_ERR, 18, 18), 326 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_UNC_ERR, 19, 19), 327 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_MH_ERR, 20, 20), 328 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_PERR, 21, 21), 329 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_PSN_ERR, 22, 22), 330 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_AV, 58, 58), 331 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_MV, 59, 59), 332 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_EN, 60, 60), 333 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_UC, 61, 61), 334 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_OVF, 62, 62), 335 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_VAL, 63, 63), 336 337 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_ADDR_CMD, 0, 5), 338 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_ADDR_ADDR, 6, 47), 339 340 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_TO, 0, 0), 341 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_DIV4, 1, 1), 342 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_TLIMIT, 2, 11), 343 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_PSN_ERR_CORR_MSK, 12, 25), 344 345 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_MORE_INFO, 0, 17), 346 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_TO_INFO, 18, 43), 347 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_SRC, 44, 45), 348 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_TID, 46, 52), 349 350 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_TO_ERR, 0, 0), 351 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_STAT_ERR, 1, 1), 352 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_DST_ERR, 2, 2), 353 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_UNC_ERR, 3, 3), 354 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_MH_ERR, 4, 4), 355 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_PERR, 5, 5), 356 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_PSN_ERR, 6, 19), 357 } tegra_ari_mca_aserr3_bitmasks_t; 358 359 typedef enum { 360 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_SERR_ERR_CODE, 0, 15), 361 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_SRC_ERR, 16, 16), 362 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_DST_ERR, 17, 17), 363 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_REQ_ERR, 18, 18), 364 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_RSP_ERR, 19, 19), 365 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_AV, 58, 58), 366 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_MV, 59, 59), 367 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_EN, 60, 60), 368 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_UC, 61, 61), 369 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_OVF, 62, 62), 370 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_VAL, 63, 63), 371 372 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_CTRL_EN_CPE_ERR, 0, 0), 373 } tegra_ari_mca_aserr4_bitmasks_t; 374 375 typedef enum { 376 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_SERR_ERR_CODE, 0, 15), 377 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_CTUPAR, 16, 16), 378 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_MULTI, 17, 17), 379 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_AV, 58, 58), 380 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_MV, 59, 59), 381 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_EN, 60, 60), 382 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_UC, 61, 61), 383 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_OVF, 62, 62), 384 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_VAL, 63, 63), 385 386 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_SRC, 0, 7), 387 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_ID, 8, 15), 388 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_DATA, 16, 26), 389 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_CMD, 32, 35), 390 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_ADDR, 36, 45), 391 392 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_CTRL_EN_CTUPAR, 0, 0), 393 } tegra_ari_mca_aserr5_bitmasks_t; 394 395 #undef TEGRA_ARI_ENUM_MASK_LSB_MSB 396 397 typedef enum { 398 TEGRA_NVG_CHANNEL_PMIC = 0, 399 TEGRA_NVG_CHANNEL_POWER_PERF = 1, 400 TEGRA_NVG_CHANNEL_POWER_MODES = 2, 401 TEGRA_NVG_CHANNEL_WAKE_TIME = 3, 402 TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, 403 TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 = 5, 404 TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC6 = 6, 405 TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC7 = 7, 406 TEGRA_NVG_CHANNEL_CROSSOVER_CCP1_CCP3 = 8, 407 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC2 = 9, 408 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC3 = 10, 409 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC4 = 11, 410 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC7 = 12, 411 TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR = 13, 412 TEGRA_NVG_CHANNEL_CSTATE_STATS_SC7_ENTRIES = 14, 413 TEGRA_NVG_CHANNEL_CSTATE_STATS_SC4_ENTRIES = 15, 414 TEGRA_NVG_CHANNEL_CSTATE_STATS_SC3_ENTRIES = 16, 415 TEGRA_NVG_CHANNEL_CSTATE_STATS_SC2_ENTRIES = 17, 416 TEGRA_NVG_CHANNEL_CSTATE_STATS_CCP3_ENTRIES = 18, 417 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC6_ENTRIES = 19, 418 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC7_ENTRIES = 20, 419 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC6_ENTRIES = 21, 420 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC7_ENTRIES = 22, 421 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_0_C6_ENTRIES = 23, 422 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_1_C6_ENTRIES = 24, 423 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_2_C6_ENTRIES = 25, /* Reserved (for Denver15 core 2) */ 424 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_3_C6_ENTRIES = 26, /* Reserved (for Denver15 core 3) */ 425 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_0_C7_ENTRIES = 27, 426 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_1_C7_ENTRIES = 28, 427 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_2_C7_ENTRIES = 29, /* Reserved (for Denver15 core 2) */ 428 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_3_C7_ENTRIES = 30, /* Reserved (for Denver15 core 3) */ 429 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_0_C7_ENTRIES = 31, 430 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_1_C7_ENTRIES = 32, 431 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_2_C7_ENTRIES = 33, 432 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_3_C7_ENTRIES = 34, 433 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_0 = 35, 434 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_1 = 36, 435 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_2 = 37, /* Reserved (for Denver15 core 2) */ 436 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_3 = 38, /* Reserved (for Denver15 core 3) */ 437 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 39, 438 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_1 = 40, 439 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_2 = 41, 440 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_3 = 42, 441 TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, 442 TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, 443 TEGRA_NVG_CHANNEL_CC3_CTRL = 45, 444 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC1 = 46, 445 TEGRA_NVG_CHANNEL_LAST_INDEX, 446 } tegra_nvg_channel_id_t; 447 448 #endif /* T18X_TEGRA_ARI_H */ 449 450 451