1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MCE_PRIVATE_H 8 #define MCE_PRIVATE_H 9 10 #include <lib/mmio.h> 11 12 #include <tegra_def.h> 13 14 /******************************************************************************* 15 * Macros to prepare CSTATE info request 16 ******************************************************************************/ 17 /* Description of the parameters for UPDATE_CSTATE_INFO request */ 18 #define CLUSTER_CSTATE_MASK ULL(0x7) 19 #define CLUSTER_CSTATE_SHIFT U(0) 20 #define CLUSTER_CSTATE_UPDATE_BIT (ULL(1) << 7) 21 #define CCPLEX_CSTATE_MASK ULL(0x3) 22 #define CCPLEX_CSTATE_SHIFT ULL(8) 23 #define CCPLEX_CSTATE_UPDATE_BIT (ULL(1) << 15) 24 #define SYSTEM_CSTATE_MASK ULL(0xF) 25 #define SYSTEM_CSTATE_SHIFT ULL(16) 26 #define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT ULL(22) 27 #define SYSTEM_CSTATE_FORCE_UPDATE_BIT (ULL(1) << 22) 28 #define SYSTEM_CSTATE_UPDATE_BIT (ULL(1) << 23) 29 #define CSTATE_WAKE_MASK_UPDATE_BIT (ULL(1) << 31) 30 #define CSTATE_WAKE_MASK_SHIFT ULL(32) 31 #define CSTATE_WAKE_MASK_CLEAR U(0xFFFFFFFF) 32 33 /******************************************************************************* 34 * Auto-CC3 control macros 35 ******************************************************************************/ 36 #define MCE_AUTO_CC3_FREQ_MASK U(0x1FF) 37 #define MCE_AUTO_CC3_FREQ_SHIFT U(0) 38 #define MCE_AUTO_CC3_VTG_MASK U(0x7F) 39 #define MCE_AUTO_CC3_VTG_SHIFT U(16) 40 #define MCE_AUTO_CC3_ENABLE_BIT (U(1) << 31) 41 42 /******************************************************************************* 43 * Macros for the 'IS_SC7_ALLOWED' command 44 ******************************************************************************/ 45 #define MCE_SC7_ALLOWED_MASK U(0x7) 46 #define MCE_SC7_WAKE_TIME_SHIFT U(32) 47 48 /******************************************************************************* 49 * Macros for 'read/write ctats' commands 50 ******************************************************************************/ 51 #define MCE_CSTATE_STATS_TYPE_SHIFT ULL(32) 52 #define MCE_CSTATE_WRITE_DATA_LO_MASK U(0xF) 53 54 /******************************************************************************* 55 * Macros for 'update crossover threshold' command 56 ******************************************************************************/ 57 #define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT U(32) 58 59 /******************************************************************************* 60 * MCA argument macros 61 ******************************************************************************/ 62 #define MCA_ARG_ERROR_MASK U(0xFF) 63 #define MCA_ARG_FINISH_SHIFT U(24) 64 #define MCA_ARG_FINISH_MASK U(0xFF) 65 66 /******************************************************************************* 67 * Uncore PERFMON ARI struct 68 ******************************************************************************/ 69 #define UNCORE_PERFMON_CMD_READ U(0) 70 #define UNCORE_PERFMON_CMD_WRITE U(1) 71 72 #define UNCORE_PERFMON_CMD_MASK U(0xFF) 73 #define UNCORE_PERFMON_CMD_SHIFT U(24) 74 #define UNCORE_PERFMON_UNIT_GRP_MASK U(0xF) 75 #define UNCORE_PERFMON_SELECTOR_MASK U(0xF) 76 #define UNCORE_PERFMON_REG_MASK U(0xFF) 77 #define UNCORE_PERFMON_CTR_MASK U(0xFF) 78 #define UNCORE_PERFMON_RESP_STATUS_MASK U(0xFF) 79 #define UNCORE_PERFMON_RESP_STATUS_SHIFT U(24) 80 81 /******************************************************************************* 82 * Structure populated by arch specific code to export routines which perform 83 * common low level MCE functions 84 ******************************************************************************/ 85 typedef struct arch_mce_ops { 86 /* 87 * This ARI request sets up the MCE to start execution on assertion 88 * of STANDBYWFI, update the core power state and expected wake time, 89 * then determine the proper power state to enter. 90 */ 91 int32_t (*enter_cstate)(uint32_t ari_base, uint32_t state, 92 uint32_t wake_time); 93 /* 94 * This ARI request allows updating of the CLUSTER_CSTATE, 95 * CCPLEX_CSTATE, and SYSTEM_CSTATE register values. 96 */ 97 int32_t (*update_cstate_info)(uint32_t ari_base, 98 uint32_t cluster, 99 uint32_t ccplex, 100 uint32_t system, 101 uint8_t sys_state_force, 102 uint32_t wake_mask, 103 uint8_t update_wake_mask); 104 /* 105 * This ARI request allows updating of power state crossover 106 * threshold times. An index value specifies which crossover 107 * state is being updated. 108 */ 109 int32_t (*update_crossover_time)(uint32_t ari_base, 110 uint32_t type, 111 uint32_t time); 112 /* 113 * This ARI request allows read access to statistical information 114 * related to power states. 115 */ 116 uint64_t (*read_cstate_stats)(uint32_t ari_base, 117 uint32_t state); 118 /* 119 * This ARI request allows write access to statistical information 120 * related to power states. 121 */ 122 int32_t (*write_cstate_stats)(uint32_t ari_base, 123 uint32_t state, 124 uint32_t stats); 125 /* 126 * This ARI request allows the CPU to understand the features 127 * supported by the MCE firmware. 128 */ 129 uint64_t (*call_enum_misc)(uint32_t ari_base, uint32_t cmd, 130 uint32_t data); 131 /* 132 * This ARI request allows querying the CCPLEX to determine if 133 * the CCx state is allowed given a target core C-state and wake 134 * time. If the CCx state is allowed, the response indicates CCx 135 * must be entered. If the CCx state is not allowed, the response 136 * indicates CC6/CC7 can't be entered 137 */ 138 int32_t (*is_ccx_allowed)(uint32_t ari_base, uint32_t state, 139 uint32_t wake_time); 140 /* 141 * This ARI request allows querying the CCPLEX to determine if 142 * the SC7 state is allowed given a target core C-state and wake 143 * time. If the SC7 state is allowed, all cores but the associated 144 * core are offlined (WAKE_EVENTS are set to 0) and the response 145 * indicates SC7 must be entered. If the SC7 state is not allowed, 146 * the response indicates SC7 can't be entered 147 */ 148 int32_t (*is_sc7_allowed)(uint32_t ari_base, uint32_t state, 149 uint32_t wake_time); 150 /* 151 * This ARI request allows a core to bring another offlined core 152 * back online to the C0 state. Note that a core is offlined by 153 * entering a C-state where the WAKE_MASK is all 0. 154 */ 155 int32_t (*online_core)(uint32_t ari_base, uint32_t cpuid); 156 /* 157 * This ARI request allows the CPU to enable/disable Auto-CC3 idle 158 * state. 159 */ 160 int32_t (*cc3_ctrl)(uint32_t ari_base, 161 uint32_t freq, 162 uint32_t volt, 163 uint8_t enable); 164 /* 165 * This ARI request allows updating the reset vector register for 166 * D15 and A57 CPUs. 167 */ 168 int32_t (*update_reset_vector)(uint32_t ari_base); 169 /* 170 * This ARI request instructs the ROC to flush A57 data caches in 171 * order to maintain coherency with the Denver cluster. 172 */ 173 int32_t (*roc_flush_cache)(uint32_t ari_base); 174 /* 175 * This ARI request instructs the ROC to flush A57 data caches along 176 * with the caches covering ARM code in order to maintain coherency 177 * with the Denver cluster. 178 */ 179 int32_t (*roc_flush_cache_trbits)(uint32_t ari_base); 180 /* 181 * This ARI request instructs the ROC to clean A57 data caches along 182 * with the caches covering ARM code in order to maintain coherency 183 * with the Denver cluster. 184 */ 185 int32_t (*roc_clean_cache)(uint32_t ari_base); 186 /* 187 * This ARI request reads/writes the Machine Check Arch. (MCA) 188 * registers. 189 */ 190 uint64_t (*read_write_mca)(uint32_t ari_base, 191 uint64_t cmd, 192 uint64_t *data); 193 /* 194 * Some MC GSC (General Security Carveout) register values are 195 * expected to be changed by TrustZone secure ARM code after boot. 196 * Since there is no hardware mechanism for the CCPLEX to know 197 * that an MC GSC register has changed to allow it to update its 198 * own internal GSC register, there needs to be a mechanism that 199 * can be used by ARM code to cause the CCPLEX to update its GSC 200 * register value. This ARI request allows updating the GSC register 201 * value for a certain carveout in the CCPLEX. 202 */ 203 int32_t (*update_ccplex_gsc)(uint32_t ari_base, uint32_t gsc_idx); 204 /* 205 * This ARI request instructs the CCPLEX to either shutdown or 206 * reset the entire system 207 */ 208 void (*enter_ccplex_state)(uint32_t ari_base, uint32_t state_idx); 209 /* 210 * This ARI request reads/writes data from/to Uncore PERFMON 211 * registers 212 */ 213 int32_t (*read_write_uncore_perfmon)(uint32_t ari_base, 214 uint64_t req, uint64_t *data); 215 /* 216 * This ARI implements ARI_MISC_CCPLEX commands. This can be 217 * used to enable/disable coresight clock gating. 218 */ 219 void (*misc_ccplex)(uint32_t ari_base, uint32_t index, 220 uint32_t value); 221 } arch_mce_ops_t; 222 223 /* declarations for ARI/NVG handler functions */ 224 int32_t ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); 225 int32_t ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, 226 uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, 227 uint8_t update_wake_mask); 228 int32_t ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); 229 uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state); 230 int32_t ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats); 231 uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data); 232 int32_t ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 233 int32_t ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 234 int32_t ari_online_core(uint32_t ari_base, uint32_t core); 235 int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); 236 int32_t ari_reset_vector_update(uint32_t ari_base); 237 int32_t ari_roc_flush_cache_trbits(uint32_t ari_base); 238 int32_t ari_roc_flush_cache(uint32_t ari_base); 239 int32_t ari_roc_clean_cache(uint32_t ari_base); 240 uint64_t ari_read_write_mca(uint32_t ari_base, uint64_t cmd, uint64_t *data); 241 int32_t ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx); 242 void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx); 243 int32_t ari_read_write_uncore_perfmon(uint32_t ari_base, 244 uint64_t req, uint64_t *data); 245 void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value); 246 247 int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); 248 int32_t nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, 249 uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, 250 uint8_t update_wake_mask); 251 int32_t nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); 252 uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state); 253 int32_t nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats); 254 int32_t nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 255 int32_t nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 256 int32_t nvg_online_core(uint32_t ari_base, uint32_t core); 257 int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); 258 259 extern void nvg_set_request_data(uint64_t req, uint64_t data); 260 extern void nvg_set_request(uint64_t req); 261 extern uint64_t nvg_get_result(void); 262 #endif /* MCE_PRIVATE_H */ 263