1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TEGRA_PRIVATE_H 8 #define TEGRA_PRIVATE_H 9 10 #include <platform_def.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <drivers/ti/uart/uart_16550.h> 15 #include <lib/psci/psci.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 18 #include <tegra_gic.h> 19 20 /******************************************************************************* 21 * Tegra DRAM memory base address 22 ******************************************************************************/ 23 #define TEGRA_DRAM_BASE ULL(0x80000000) 24 #define TEGRA_DRAM_END ULL(0x27FFFFFFF) 25 26 /******************************************************************************* 27 * Implementation defined ACTLR_EL1 bit definitions 28 ******************************************************************************/ 29 #define ACTLR_EL1_PMSTATE_MASK (ULL(0xF) << 0) 30 31 /******************************************************************************* 32 * Implementation defined ACTLR_EL2 bit definitions 33 ******************************************************************************/ 34 #define ACTLR_EL2_PMSTATE_MASK (ULL(0xF) << 0) 35 36 /******************************************************************************* 37 * Struct for parameters received from BL2 38 ******************************************************************************/ 39 typedef struct plat_params_from_bl2 { 40 /* TZ memory size */ 41 uint64_t tzdram_size; 42 /* TZ memory base */ 43 uint64_t tzdram_base; 44 /* UART port ID */ 45 int32_t uart_id; 46 /* L2 ECC parity protection disable flag */ 47 int32_t l2_ecc_parity_prot_dis; 48 /* SHMEM base address for storing the boot logs */ 49 uint64_t boot_profiler_shmem_base; 50 /* System Suspend Entry Firmware size */ 51 uint64_t sc7entry_fw_size; 52 /* System Suspend Entry Firmware base address */ 53 uint64_t sc7entry_fw_base; 54 } plat_params_from_bl2_t; 55 56 /******************************************************************************* 57 * Helper function to access l2ctlr_el1 register on Cortex-A57 CPUs 58 ******************************************************************************/ 59 DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1) 60 61 /******************************************************************************* 62 * Struct describing parameters passed to bl31 63 ******************************************************************************/ 64 struct tegra_bl31_params { 65 param_header_t h; 66 image_info_t *bl31_image_info; 67 entry_point_info_t *bl32_ep_info; 68 image_info_t *bl32_image_info; 69 entry_point_info_t *bl33_ep_info; 70 image_info_t *bl33_image_info; 71 }; 72 73 /* Declarations for plat_psci_handlers.c */ 74 int32_t tegra_soc_validate_power_state(uint32_t power_state, 75 psci_power_state_t *req_state); 76 77 /* Declarations for plat_setup.c */ 78 const mmap_region_t *plat_get_mmio_map(void); 79 uint32_t plat_get_console_from_id(int32_t id); 80 void plat_gic_setup(void); 81 struct tegra_bl31_params *plat_get_bl31_params(void); 82 plat_params_from_bl2_t *plat_get_bl31_plat_params(void); 83 void plat_early_platform_setup(void); 84 void plat_late_platform_setup(void); 85 86 /* Declarations for plat_secondary.c */ 87 void plat_secondary_setup(void); 88 int32_t plat_lock_cpu_vectors(void); 89 90 /* Declarations for tegra_fiq_glue.c */ 91 void tegra_fiq_handler_setup(void); 92 int tegra_fiq_get_intr_context(void); 93 void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); 94 95 /* Declarations for tegra_security.c */ 96 void tegra_security_setup(void); 97 void tegra_security_setup_videomem(uintptr_t base, uint64_t size); 98 99 /* Declarations for tegra_pm.c */ 100 extern uint8_t tegra_fake_system_suspend; 101 102 void tegra_pm_system_suspend_entry(void); 103 void tegra_pm_system_suspend_exit(void); 104 int32_t tegra_system_suspended(void); 105 int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state); 106 int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state); 107 int32_t tegra_soc_pwr_domain_on(u_register_t mpidr); 108 int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state); 109 int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state); 110 int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); 111 int32_t tegra_soc_prepare_system_reset(void); 112 __dead2 void tegra_soc_prepare_system_off(void); 113 plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, 114 const plat_local_state_t *states, 115 uint32_t ncpu); 116 void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state); 117 void tegra_cpu_standby(plat_local_state_t cpu_state); 118 int32_t tegra_pwr_domain_on(u_register_t mpidr); 119 void tegra_pwr_domain_off(const psci_power_state_t *target_state); 120 void tegra_pwr_domain_suspend(const psci_power_state_t *target_state); 121 void __dead2 tegra_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); 122 void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state); 123 void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state); 124 __dead2 void tegra_system_off(void); 125 __dead2 void tegra_system_reset(void); 126 int32_t tegra_validate_power_state(uint32_t power_state, 127 psci_power_state_t *req_state); 128 int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint); 129 130 /* Declarations for tegraXXX_pm.c */ 131 int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); 132 int tegra_prepare_cpu_on_finish(unsigned long mpidr); 133 134 /* Declarations for tegra_bl31_setup.c */ 135 plat_params_from_bl2_t *bl31_get_plat_params(void); 136 int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); 137 138 /* Declarations for tegra_delay_timer.c */ 139 void tegra_delay_timer_init(void); 140 141 void tegra_secure_entrypoint(void); 142 void tegra186_cpu_reset_handler(void); 143 144 /* Declarations for tegra_sip_calls.c */ 145 uintptr_t tegra_sip_handler(uint32_t smc_fid, 146 u_register_t x1, 147 u_register_t x2, 148 u_register_t x3, 149 u_register_t x4, 150 void *cookie, 151 void *handle, 152 u_register_t flags); 153 int plat_sip_handler(uint32_t smc_fid, 154 uint64_t x1, 155 uint64_t x2, 156 uint64_t x3, 157 uint64_t x4, 158 const void *cookie, 159 void *handle, 160 uint64_t flags); 161 162 #endif /* TEGRA_PRIVATE_H */ 163