1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef TEGRA_PRIVATE_H 9 #define TEGRA_PRIVATE_H 10 11 #include <platform_def.h> 12 #include <stdbool.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <drivers/ti/uart/uart_16550.h> 17 #include <lib/psci/psci.h> 18 #include <lib/xlat_tables/xlat_tables_v2.h> 19 20 #include <tegra_gic.h> 21 22 /******************************************************************************* 23 * Implementation defined ACTLR_EL1 bit definitions 24 ******************************************************************************/ 25 #define ACTLR_EL1_PMSTATE_MASK (ULL(0xF) << 0) 26 27 /******************************************************************************* 28 * Implementation defined ACTLR_EL2 bit definitions 29 ******************************************************************************/ 30 #define ACTLR_EL2_PMSTATE_MASK (ULL(0xF) << 0) 31 32 /******************************************************************************* 33 * Struct for parameters received from BL2 34 ******************************************************************************/ 35 typedef struct plat_params_from_bl2 { 36 /* TZ memory size */ 37 uint64_t tzdram_size; 38 /* TZ memory base */ 39 uint64_t tzdram_base; 40 /* UART port ID */ 41 int32_t uart_id; 42 /* L2 ECC parity protection disable flag */ 43 int32_t l2_ecc_parity_prot_dis; 44 /* SHMEM base address for storing the boot logs */ 45 uint64_t boot_profiler_shmem_base; 46 /* System Suspend Entry Firmware size */ 47 uint64_t sc7entry_fw_size; 48 /* System Suspend Entry Firmware base address */ 49 uint64_t sc7entry_fw_base; 50 } plat_params_from_bl2_t; 51 52 /******************************************************************************* 53 * Helper function to access l2ctlr_el1 register on Cortex-A57 CPUs 54 ******************************************************************************/ 55 DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1) 56 57 /******************************************************************************* 58 * Struct describing parameters passed to bl31 59 ******************************************************************************/ 60 struct tegra_bl31_params { 61 param_header_t h; 62 image_info_t *bl31_image_info; 63 entry_point_info_t *bl32_ep_info; 64 image_info_t *bl32_image_info; 65 entry_point_info_t *bl33_ep_info; 66 image_info_t *bl33_image_info; 67 }; 68 69 /* Declarations for plat_psci_handlers.c */ 70 int32_t tegra_soc_validate_power_state(uint32_t power_state, 71 psci_power_state_t *req_state); 72 73 /* Declarations for plat_setup.c */ 74 const mmap_region_t *plat_get_mmio_map(void); 75 void plat_enable_console(int32_t id); 76 void plat_gic_setup(void); 77 struct tegra_bl31_params *plat_get_bl31_params(void); 78 plat_params_from_bl2_t *plat_get_bl31_plat_params(void); 79 void plat_early_platform_setup(void); 80 void plat_late_platform_setup(void); 81 void plat_relocate_bl32_image(const image_info_t *bl32_img_info); 82 bool plat_supports_system_suspend(void); 83 84 /* Declarations for plat_secondary.c */ 85 void plat_secondary_setup(void); 86 int32_t plat_lock_cpu_vectors(void); 87 88 /* Declarations for tegra_fiq_glue.c */ 89 void tegra_fiq_handler_setup(void); 90 int tegra_fiq_get_intr_context(void); 91 void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); 92 93 /* Declarations for tegra_security.c */ 94 void tegra_security_setup(void); 95 void tegra_security_setup_videomem(uintptr_t base, uint64_t size); 96 97 /* Declarations for tegra_pm.c */ 98 void tegra_pm_system_suspend_entry(void); 99 void tegra_pm_system_suspend_exit(void); 100 int32_t tegra_system_suspended(void); 101 int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state); 102 int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state); 103 int32_t tegra_soc_pwr_domain_on(u_register_t mpidr); 104 int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state); 105 int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state); 106 int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); 107 int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state); 108 int32_t tegra_soc_prepare_system_reset(void); 109 __dead2 void tegra_soc_prepare_system_off(void); 110 plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, 111 const plat_local_state_t *states, 112 uint32_t ncpu); 113 void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state); 114 void tegra_cpu_standby(plat_local_state_t cpu_state); 115 int32_t tegra_pwr_domain_on(u_register_t mpidr); 116 void tegra_pwr_domain_off(const psci_power_state_t *target_state); 117 void tegra_pwr_domain_suspend(const psci_power_state_t *target_state); 118 void __dead2 tegra_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); 119 void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state); 120 void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state); 121 __dead2 void tegra_system_off(void); 122 __dead2 void tegra_system_reset(void); 123 int32_t tegra_validate_power_state(uint32_t power_state, 124 psci_power_state_t *req_state); 125 int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint); 126 127 /* Declarations for tegraXXX_pm.c */ 128 int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); 129 int tegra_prepare_cpu_on_finish(unsigned long mpidr); 130 131 /* Declarations for tegra_bl31_setup.c */ 132 plat_params_from_bl2_t *bl31_get_plat_params(void); 133 int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); 134 135 /* Declarations for tegra_delay_timer.c */ 136 void tegra_delay_timer_init(void); 137 138 void tegra_secure_entrypoint(void); 139 140 /* Declarations for tegra_sip_calls.c */ 141 uintptr_t tegra_sip_handler(uint32_t smc_fid, 142 u_register_t x1, 143 u_register_t x2, 144 u_register_t x3, 145 u_register_t x4, 146 void *cookie, 147 void *handle, 148 u_register_t flags); 149 int plat_sip_handler(uint32_t smc_fid, 150 uint64_t x1, 151 uint64_t x2, 152 uint64_t x3, 153 uint64_t x4, 154 const void *cookie, 155 void *handle, 156 uint64_t flags); 157 158 #endif /* TEGRA_PRIVATE_H */ 159