xref: /rk3399_ARM-atf/plat/nvidia/tegra/include/tegra_private.h (revision 93eafbcad46b83bb0db3b86b1508f08efce25519)
108438e24SVarun Wadekar /*
208438e24SVarun Wadekar  * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
308438e24SVarun Wadekar  *
408438e24SVarun Wadekar  * Redistribution and use in source and binary forms, with or without
508438e24SVarun Wadekar  * modification, are permitted provided that the following conditions are met:
608438e24SVarun Wadekar  *
708438e24SVarun Wadekar  * Redistributions of source code must retain the above copyright notice, this
808438e24SVarun Wadekar  * list of conditions and the following disclaimer.
908438e24SVarun Wadekar  *
1008438e24SVarun Wadekar  * Redistributions in binary form must reproduce the above copyright notice,
1108438e24SVarun Wadekar  * this list of conditions and the following disclaimer in the documentation
1208438e24SVarun Wadekar  * and/or other materials provided with the distribution.
1308438e24SVarun Wadekar  *
1408438e24SVarun Wadekar  * Neither the name of ARM nor the names of its contributors may be used
1508438e24SVarun Wadekar  * to endorse or promote products derived from this software without specific
1608438e24SVarun Wadekar  * prior written permission.
1708438e24SVarun Wadekar  *
1808438e24SVarun Wadekar  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
1908438e24SVarun Wadekar  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2008438e24SVarun Wadekar  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2108438e24SVarun Wadekar  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
2208438e24SVarun Wadekar  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2308438e24SVarun Wadekar  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2408438e24SVarun Wadekar  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2508438e24SVarun Wadekar  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2608438e24SVarun Wadekar  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2708438e24SVarun Wadekar  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
2808438e24SVarun Wadekar  * POSSIBILITY OF SUCH DAMAGE.
2908438e24SVarun Wadekar  */
3008438e24SVarun Wadekar 
3108438e24SVarun Wadekar #ifndef __TEGRA_PRIVATE_H__
3208438e24SVarun Wadekar #define __TEGRA_PRIVATE_H__
3308438e24SVarun Wadekar 
3408438e24SVarun Wadekar #include <xlat_tables.h>
3508438e24SVarun Wadekar #include <platform_def.h>
3608438e24SVarun Wadekar 
379a964510SVarun Wadekar /*******************************************************************************
389a964510SVarun Wadekar  * Tegra DRAM memory base address
399a964510SVarun Wadekar  ******************************************************************************/
409a964510SVarun Wadekar #define TEGRA_DRAM_BASE		0x80000000
419a964510SVarun Wadekar #define TEGRA_DRAM_END		0x27FFFFFFF
429a964510SVarun Wadekar 
4308438e24SVarun Wadekar typedef struct plat_params_from_bl2 {
4408438e24SVarun Wadekar 	uint64_t tzdram_size;
4508438e24SVarun Wadekar 	uintptr_t bl32_params;
4608438e24SVarun Wadekar } plat_params_from_bl2_t;
4708438e24SVarun Wadekar 
48*93eafbcaSVarun Wadekar /* Declarations for plat_psci_handlers.c */
49*93eafbcaSVarun Wadekar int32_t tegra_soc_validate_power_state(unsigned int power_state);
50*93eafbcaSVarun Wadekar 
5108438e24SVarun Wadekar /* Declarations for plat_setup.c */
5208438e24SVarun Wadekar const mmap_region_t *plat_get_mmio_map(void);
5308438e24SVarun Wadekar uint64_t plat_get_syscnt_freq(void);
5408438e24SVarun Wadekar 
5508438e24SVarun Wadekar /* Declarations for plat_secondary.c */
5608438e24SVarun Wadekar void plat_secondary_setup(void);
5708438e24SVarun Wadekar int plat_lock_cpu_vectors(void);
5808438e24SVarun Wadekar 
5908438e24SVarun Wadekar /* Declarations for tegra_gic.c */
6008438e24SVarun Wadekar void tegra_gic_setup(void);
6108438e24SVarun Wadekar void tegra_gic_cpuif_deactivate(void);
6208438e24SVarun Wadekar 
6308438e24SVarun Wadekar /* Declarations for tegra_security.c */
6408438e24SVarun Wadekar void tegra_security_setup(void);
6508438e24SVarun Wadekar void tegra_security_setup_videomem(uintptr_t base, uint64_t size);
6608438e24SVarun Wadekar 
6708438e24SVarun Wadekar /* Declarations for tegra_pm.c */
6808438e24SVarun Wadekar void tegra_pm_system_suspend_entry(void);
6908438e24SVarun Wadekar void tegra_pm_system_suspend_exit(void);
7008438e24SVarun Wadekar int tegra_system_suspended(void);
7108438e24SVarun Wadekar 
7208438e24SVarun Wadekar /* Declarations for tegraXXX_pm.c */
7308438e24SVarun Wadekar int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl);
7408438e24SVarun Wadekar int tegra_prepare_cpu_on_finish(unsigned long mpidr);
7508438e24SVarun Wadekar 
7608438e24SVarun Wadekar /* Declarations for tegra_bl31_setup.c */
7708438e24SVarun Wadekar plat_params_from_bl2_t *bl31_get_plat_params(void);
789a964510SVarun Wadekar int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes);
7908438e24SVarun Wadekar 
80c8961326SVarun Wadekar /* Declarations for tegra_delay_timer.c */
81c8961326SVarun Wadekar void tegra_delay_timer_init(void);
82c8961326SVarun Wadekar 
8308438e24SVarun Wadekar #endif /* __TEGRA_PRIVATE_H__ */
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