108438e24SVarun Wadekar /* 2d3360301SVarun Wadekar * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 408438e24SVarun Wadekar * Redistribution and use in source and binary forms, with or without 508438e24SVarun Wadekar * modification, are permitted provided that the following conditions are met: 608438e24SVarun Wadekar * 708438e24SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 808438e24SVarun Wadekar * list of conditions and the following disclaimer. 908438e24SVarun Wadekar * 1008438e24SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 1108438e24SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 1208438e24SVarun Wadekar * and/or other materials provided with the distribution. 1308438e24SVarun Wadekar * 1408438e24SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 1508438e24SVarun Wadekar * to endorse or promote products derived from this software without specific 1608438e24SVarun Wadekar * prior written permission. 1708438e24SVarun Wadekar * 1808438e24SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1908438e24SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2008438e24SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2108438e24SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2208438e24SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2308438e24SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2408438e24SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2508438e24SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2608438e24SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2708438e24SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2808438e24SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 2908438e24SVarun Wadekar */ 3008438e24SVarun Wadekar 3108438e24SVarun Wadekar #ifndef __TEGRA_PRIVATE_H__ 3208438e24SVarun Wadekar #define __TEGRA_PRIVATE_H__ 3308438e24SVarun Wadekar 3471cb26eaSVarun Wadekar #include <arch.h> 3508438e24SVarun Wadekar #include <platform_def.h> 36ca8b7d51SYatharth Kochar #include <psci.h> 3771cb26eaSVarun Wadekar #include <xlat_tables.h> 3808438e24SVarun Wadekar 399a964510SVarun Wadekar /******************************************************************************* 409a964510SVarun Wadekar * Tegra DRAM memory base address 419a964510SVarun Wadekar ******************************************************************************/ 429a964510SVarun Wadekar #define TEGRA_DRAM_BASE 0x80000000 439a964510SVarun Wadekar #define TEGRA_DRAM_END 0x27FFFFFFF 449a964510SVarun Wadekar 45d3360301SVarun Wadekar /******************************************************************************* 46d3360301SVarun Wadekar * Struct for parameters received from BL2 47d3360301SVarun Wadekar ******************************************************************************/ 4808438e24SVarun Wadekar typedef struct plat_params_from_bl2 { 49e0d4158cSVarun Wadekar /* TZ memory size */ 5008438e24SVarun Wadekar uint64_t tzdram_size; 51e0d4158cSVarun Wadekar /* TZ memory base */ 52e0d4158cSVarun Wadekar uint64_t tzdram_base; 53e1084216SVarun Wadekar /* UART port ID */ 54e1084216SVarun Wadekar int uart_id; 5508438e24SVarun Wadekar } plat_params_from_bl2_t; 5608438e24SVarun Wadekar 57*78e2bd10SVarun Wadekar /******************************************************************************* 58*78e2bd10SVarun Wadekar * Per-CPU struct describing FIQ state to be stored 59*78e2bd10SVarun Wadekar ******************************************************************************/ 60*78e2bd10SVarun Wadekar typedef struct pcpu_fiq_state { 61*78e2bd10SVarun Wadekar uint64_t elr_el3; 62*78e2bd10SVarun Wadekar uint64_t spsr_el3; 63*78e2bd10SVarun Wadekar } pcpu_fiq_state_t; 64*78e2bd10SVarun Wadekar 6593eafbcaSVarun Wadekar /* Declarations for plat_psci_handlers.c */ 6671cb26eaSVarun Wadekar int32_t tegra_soc_validate_power_state(unsigned int power_state, 6771cb26eaSVarun Wadekar psci_power_state_t *req_state); 6893eafbcaSVarun Wadekar 6908438e24SVarun Wadekar /* Declarations for plat_setup.c */ 7008438e24SVarun Wadekar const mmap_region_t *plat_get_mmio_map(void); 71e1084216SVarun Wadekar uint32_t plat_get_console_from_id(int id); 72d3360301SVarun Wadekar void plat_gic_setup(void); 7308438e24SVarun Wadekar 7408438e24SVarun Wadekar /* Declarations for plat_secondary.c */ 7508438e24SVarun Wadekar void plat_secondary_setup(void); 7608438e24SVarun Wadekar int plat_lock_cpu_vectors(void); 7708438e24SVarun Wadekar 78*78e2bd10SVarun Wadekar /* Declarations for tegra_fiq_glue.c */ 79*78e2bd10SVarun Wadekar void tegra_fiq_handler_setup(void); 80*78e2bd10SVarun Wadekar int tegra_fiq_get_intr_context(void); 81*78e2bd10SVarun Wadekar void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); 82*78e2bd10SVarun Wadekar 8308438e24SVarun Wadekar /* Declarations for tegra_gic.c */ 84d3360301SVarun Wadekar void tegra_gic_setup(const unsigned int *irq_sec_ptr, unsigned int num_irqs); 8508438e24SVarun Wadekar void tegra_gic_cpuif_deactivate(void); 8608438e24SVarun Wadekar 8708438e24SVarun Wadekar /* Declarations for tegra_security.c */ 8808438e24SVarun Wadekar void tegra_security_setup(void); 8908438e24SVarun Wadekar void tegra_security_setup_videomem(uintptr_t base, uint64_t size); 9008438e24SVarun Wadekar 9108438e24SVarun Wadekar /* Declarations for tegra_pm.c */ 9208438e24SVarun Wadekar void tegra_pm_system_suspend_entry(void); 9308438e24SVarun Wadekar void tegra_pm_system_suspend_exit(void); 9408438e24SVarun Wadekar int tegra_system_suspended(void); 9508438e24SVarun Wadekar 9608438e24SVarun Wadekar /* Declarations for tegraXXX_pm.c */ 9708438e24SVarun Wadekar int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); 9808438e24SVarun Wadekar int tegra_prepare_cpu_on_finish(unsigned long mpidr); 9908438e24SVarun Wadekar 10008438e24SVarun Wadekar /* Declarations for tegra_bl31_setup.c */ 10108438e24SVarun Wadekar plat_params_from_bl2_t *bl31_get_plat_params(void); 1029a964510SVarun Wadekar int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); 1035ea0b028SVarun Wadekar void plat_early_platform_setup(void); 10408438e24SVarun Wadekar 105c8961326SVarun Wadekar /* Declarations for tegra_delay_timer.c */ 106c8961326SVarun Wadekar void tegra_delay_timer_init(void); 107c8961326SVarun Wadekar 10808438e24SVarun Wadekar #endif /* __TEGRA_PRIVATE_H__ */ 109