108438e24SVarun Wadekar /* 2544c092bSAmbroise Vincent * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3e44f86efSVarun Wadekar * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 408438e24SVarun Wadekar * 582cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 608438e24SVarun Wadekar */ 708438e24SVarun Wadekar 8c3cf06f1SAntonio Nino Diaz #ifndef TEGRA_PRIVATE_H 9c3cf06f1SAntonio Nino Diaz #define TEGRA_PRIVATE_H 1008438e24SVarun Wadekar 1109d40e0eSAntonio Nino Diaz #include <platform_def.h> 12*5d52aea8SVarun Wadekar #include <stdbool.h> 1309d40e0eSAntonio Nino Diaz 1471cb26eaSVarun Wadekar #include <arch.h> 1580c50eeaSVarun Wadekar #include <arch_helpers.h> 16544c092bSAmbroise Vincent #include <drivers/ti/uart/uart_16550.h> 1709d40e0eSAntonio Nino Diaz #include <lib/psci/psci.h> 1809d40e0eSAntonio Nino Diaz #include <lib/xlat_tables/xlat_tables_v2.h> 1909d40e0eSAntonio Nino Diaz 2080c50eeaSVarun Wadekar #include <tegra_gic.h> 2108438e24SVarun Wadekar 229a964510SVarun Wadekar /******************************************************************************* 2375516c3eSSteven Kao * Implementation defined ACTLR_EL1 bit definitions 2475516c3eSSteven Kao ******************************************************************************/ 2575516c3eSSteven Kao #define ACTLR_EL1_PMSTATE_MASK (ULL(0xF) << 0) 2675516c3eSSteven Kao 2775516c3eSSteven Kao /******************************************************************************* 2875516c3eSSteven Kao * Implementation defined ACTLR_EL2 bit definitions 2975516c3eSSteven Kao ******************************************************************************/ 3075516c3eSSteven Kao #define ACTLR_EL2_PMSTATE_MASK (ULL(0xF) << 0) 3175516c3eSSteven Kao 3275516c3eSSteven Kao /******************************************************************************* 33d3360301SVarun Wadekar * Struct for parameters received from BL2 34d3360301SVarun Wadekar ******************************************************************************/ 3508438e24SVarun Wadekar typedef struct plat_params_from_bl2 { 36e0d4158cSVarun Wadekar /* TZ memory size */ 3708438e24SVarun Wadekar uint64_t tzdram_size; 38e0d4158cSVarun Wadekar /* TZ memory base */ 39e0d4158cSVarun Wadekar uint64_t tzdram_base; 40e1084216SVarun Wadekar /* UART port ID */ 41fcf23a14SVarun Wadekar int32_t uart_id; 42b495791bSHarvey Hsieh /* L2 ECC parity protection disable flag */ 43fcf23a14SVarun Wadekar int32_t l2_ecc_parity_prot_dis; 44087cf68aSVarun Wadekar /* SHMEM base address for storing the boot logs */ 45087cf68aSVarun Wadekar uint64_t boot_profiler_shmem_base; 463ca3c27cSVarun Wadekar /* System Suspend Entry Firmware size */ 473ca3c27cSVarun Wadekar uint64_t sc7entry_fw_size; 483ca3c27cSVarun Wadekar /* System Suspend Entry Firmware base address */ 493ca3c27cSVarun Wadekar uint64_t sc7entry_fw_base; 5008438e24SVarun Wadekar } plat_params_from_bl2_t; 5108438e24SVarun Wadekar 5278e2bd10SVarun Wadekar /******************************************************************************* 53b495791bSHarvey Hsieh * Helper function to access l2ctlr_el1 register on Cortex-A57 CPUs 54b495791bSHarvey Hsieh ******************************************************************************/ 55b495791bSHarvey Hsieh DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1) 56b495791bSHarvey Hsieh 57b495791bSHarvey Hsieh /******************************************************************************* 58fdcc1127SAntonio Nino Diaz * Struct describing parameters passed to bl31 59fdcc1127SAntonio Nino Diaz ******************************************************************************/ 60fdcc1127SAntonio Nino Diaz struct tegra_bl31_params { 61fdcc1127SAntonio Nino Diaz param_header_t h; 62fdcc1127SAntonio Nino Diaz image_info_t *bl31_image_info; 63fdcc1127SAntonio Nino Diaz entry_point_info_t *bl32_ep_info; 64fdcc1127SAntonio Nino Diaz image_info_t *bl32_image_info; 65fdcc1127SAntonio Nino Diaz entry_point_info_t *bl33_ep_info; 66fdcc1127SAntonio Nino Diaz image_info_t *bl33_image_info; 67fdcc1127SAntonio Nino Diaz }; 68fdcc1127SAntonio Nino Diaz 6993eafbcaSVarun Wadekar /* Declarations for plat_psci_handlers.c */ 70214e8464SAnthony Zhou int32_t tegra_soc_validate_power_state(uint32_t power_state, 7171cb26eaSVarun Wadekar psci_power_state_t *req_state); 7293eafbcaSVarun Wadekar 7308438e24SVarun Wadekar /* Declarations for plat_setup.c */ 7408438e24SVarun Wadekar const mmap_region_t *plat_get_mmio_map(void); 75117dbe6cSVarun Wadekar void plat_enable_console(int32_t id); 76d3360301SVarun Wadekar void plat_gic_setup(void); 77fdcc1127SAntonio Nino Diaz struct tegra_bl31_params *plat_get_bl31_params(void); 788ab06d2fSVarun Wadekar plat_params_from_bl2_t *plat_get_bl31_plat_params(void); 793e1923d9SDilan Lee void plat_early_platform_setup(void); 803e1923d9SDilan Lee void plat_late_platform_setup(void); 816f47acdbSVarun Wadekar void plat_relocate_bl32_image(const image_info_t *bl32_img_info); 82*5d52aea8SVarun Wadekar bool plat_supports_system_suspend(void); 8308438e24SVarun Wadekar 8408438e24SVarun Wadekar /* Declarations for plat_secondary.c */ 8508438e24SVarun Wadekar void plat_secondary_setup(void); 86592035d0SAnthony Zhou int32_t plat_lock_cpu_vectors(void); 8708438e24SVarun Wadekar 8878e2bd10SVarun Wadekar /* Declarations for tegra_fiq_glue.c */ 8978e2bd10SVarun Wadekar void tegra_fiq_handler_setup(void); 9078e2bd10SVarun Wadekar int tegra_fiq_get_intr_context(void); 9178e2bd10SVarun Wadekar void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); 9278e2bd10SVarun Wadekar 9308438e24SVarun Wadekar /* Declarations for tegra_security.c */ 9408438e24SVarun Wadekar void tegra_security_setup(void); 9508438e24SVarun Wadekar void tegra_security_setup_videomem(uintptr_t base, uint64_t size); 9608438e24SVarun Wadekar 9708438e24SVarun Wadekar /* Declarations for tegra_pm.c */ 9808438e24SVarun Wadekar void tegra_pm_system_suspend_entry(void); 9908438e24SVarun Wadekar void tegra_pm_system_suspend_exit(void); 100b36aea5aSAnthony Zhou int32_t tegra_system_suspended(void); 1010887026eSVarun Wadekar int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state); 102b36aea5aSAnthony Zhou int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state); 103b36aea5aSAnthony Zhou int32_t tegra_soc_pwr_domain_on(u_register_t mpidr); 104b36aea5aSAnthony Zhou int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state); 105b36aea5aSAnthony Zhou int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state); 106b36aea5aSAnthony Zhou int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); 107e44f86efSVarun Wadekar int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state); 108b36aea5aSAnthony Zhou int32_t tegra_soc_prepare_system_reset(void); 109b36aea5aSAnthony Zhou __dead2 void tegra_soc_prepare_system_off(void); 110b36aea5aSAnthony Zhou plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, 111b36aea5aSAnthony Zhou const plat_local_state_t *states, 112b36aea5aSAnthony Zhou uint32_t ncpu); 113b36aea5aSAnthony Zhou void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state); 114b36aea5aSAnthony Zhou void tegra_cpu_standby(plat_local_state_t cpu_state); 115b36aea5aSAnthony Zhou int32_t tegra_pwr_domain_on(u_register_t mpidr); 116b36aea5aSAnthony Zhou void tegra_pwr_domain_off(const psci_power_state_t *target_state); 117b36aea5aSAnthony Zhou void tegra_pwr_domain_suspend(const psci_power_state_t *target_state); 118b36aea5aSAnthony Zhou void __dead2 tegra_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); 119b36aea5aSAnthony Zhou void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state); 120b36aea5aSAnthony Zhou void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state); 121b36aea5aSAnthony Zhou __dead2 void tegra_system_off(void); 122b36aea5aSAnthony Zhou __dead2 void tegra_system_reset(void); 123b36aea5aSAnthony Zhou int32_t tegra_validate_power_state(uint32_t power_state, 124b36aea5aSAnthony Zhou psci_power_state_t *req_state); 125b36aea5aSAnthony Zhou int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint); 12608438e24SVarun Wadekar 12708438e24SVarun Wadekar /* Declarations for tegraXXX_pm.c */ 12808438e24SVarun Wadekar int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); 12908438e24SVarun Wadekar int tegra_prepare_cpu_on_finish(unsigned long mpidr); 13008438e24SVarun Wadekar 13108438e24SVarun Wadekar /* Declarations for tegra_bl31_setup.c */ 13208438e24SVarun Wadekar plat_params_from_bl2_t *bl31_get_plat_params(void); 133fcf23a14SVarun Wadekar int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); 13408438e24SVarun Wadekar 135c8961326SVarun Wadekar /* Declarations for tegra_delay_timer.c */ 136c8961326SVarun Wadekar void tegra_delay_timer_init(void); 137c8961326SVarun Wadekar 13868c7de6fSVarun Wadekar void tegra_secure_entrypoint(void); 13968c7de6fSVarun Wadekar 1401d49112bSAnthony Zhou /* Declarations for tegra_sip_calls.c */ 1411d49112bSAnthony Zhou uintptr_t tegra_sip_handler(uint32_t smc_fid, 1421d49112bSAnthony Zhou u_register_t x1, 1431d49112bSAnthony Zhou u_register_t x2, 1441d49112bSAnthony Zhou u_register_t x3, 1451d49112bSAnthony Zhou u_register_t x4, 1461d49112bSAnthony Zhou void *cookie, 1471d49112bSAnthony Zhou void *handle, 1481d49112bSAnthony Zhou u_register_t flags); 1491d49112bSAnthony Zhou int plat_sip_handler(uint32_t smc_fid, 1501d49112bSAnthony Zhou uint64_t x1, 1511d49112bSAnthony Zhou uint64_t x2, 1521d49112bSAnthony Zhou uint64_t x3, 1531d49112bSAnthony Zhou uint64_t x4, 1541d49112bSAnthony Zhou const void *cookie, 1551d49112bSAnthony Zhou void *handle, 1561d49112bSAnthony Zhou uint64_t flags); 1571d49112bSAnthony Zhou 158c3cf06f1SAntonio Nino Diaz #endif /* TEGRA_PRIVATE_H */ 159