108438e24SVarun Wadekar /* 250e91633SAnthony Zhou * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 7c3cf06f1SAntonio Nino Diaz #ifndef TEGRA_PRIVATE_H 8c3cf06f1SAntonio Nino Diaz #define TEGRA_PRIVATE_H 908438e24SVarun Wadekar 1009d40e0eSAntonio Nino Diaz #include <platform_def.h> 1109d40e0eSAntonio Nino Diaz 1271cb26eaSVarun Wadekar #include <arch.h> 1380c50eeaSVarun Wadekar #include <arch_helpers.h> 1409d40e0eSAntonio Nino Diaz #include <lib/psci/psci.h> 1509d40e0eSAntonio Nino Diaz #include <lib/xlat_tables/xlat_tables_v2.h> 1609d40e0eSAntonio Nino Diaz 1780c50eeaSVarun Wadekar #include <tegra_gic.h> 1808438e24SVarun Wadekar 199a964510SVarun Wadekar /******************************************************************************* 209a964510SVarun Wadekar * Tegra DRAM memory base address 219a964510SVarun Wadekar ******************************************************************************/ 2270cb692eSVarun Wadekar #define TEGRA_DRAM_BASE ULL(0x80000000) 2370cb692eSVarun Wadekar #define TEGRA_DRAM_END ULL(0x27FFFFFFF) 249a964510SVarun Wadekar 25d3360301SVarun Wadekar /******************************************************************************* 2675516c3eSSteven Kao * Implementation defined ACTLR_EL1 bit definitions 2775516c3eSSteven Kao ******************************************************************************/ 2875516c3eSSteven Kao #define ACTLR_EL1_PMSTATE_MASK (ULL(0xF) << 0) 2975516c3eSSteven Kao 3075516c3eSSteven Kao /******************************************************************************* 3175516c3eSSteven Kao * Implementation defined ACTLR_EL2 bit definitions 3275516c3eSSteven Kao ******************************************************************************/ 3375516c3eSSteven Kao #define ACTLR_EL2_PMSTATE_MASK (ULL(0xF) << 0) 3475516c3eSSteven Kao 3575516c3eSSteven Kao /******************************************************************************* 36d3360301SVarun Wadekar * Struct for parameters received from BL2 37d3360301SVarun Wadekar ******************************************************************************/ 3808438e24SVarun Wadekar typedef struct plat_params_from_bl2 { 39e0d4158cSVarun Wadekar /* TZ memory size */ 4008438e24SVarun Wadekar uint64_t tzdram_size; 41e0d4158cSVarun Wadekar /* TZ memory base */ 42e0d4158cSVarun Wadekar uint64_t tzdram_base; 43e1084216SVarun Wadekar /* UART port ID */ 44fcf23a14SVarun Wadekar int32_t uart_id; 45b495791bSHarvey Hsieh /* L2 ECC parity protection disable flag */ 46fcf23a14SVarun Wadekar int32_t l2_ecc_parity_prot_dis; 47087cf68aSVarun Wadekar /* SHMEM base address for storing the boot logs */ 48087cf68aSVarun Wadekar uint64_t boot_profiler_shmem_base; 49*3ca3c27cSVarun Wadekar /* System Suspend Entry Firmware size */ 50*3ca3c27cSVarun Wadekar uint64_t sc7entry_fw_size; 51*3ca3c27cSVarun Wadekar /* System Suspend Entry Firmware base address */ 52*3ca3c27cSVarun Wadekar uint64_t sc7entry_fw_base; 5308438e24SVarun Wadekar } plat_params_from_bl2_t; 5408438e24SVarun Wadekar 5578e2bd10SVarun Wadekar /******************************************************************************* 56b495791bSHarvey Hsieh * Helper function to access l2ctlr_el1 register on Cortex-A57 CPUs 57b495791bSHarvey Hsieh ******************************************************************************/ 58b495791bSHarvey Hsieh DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1) 59b495791bSHarvey Hsieh 60b495791bSHarvey Hsieh /******************************************************************************* 61fdcc1127SAntonio Nino Diaz * Struct describing parameters passed to bl31 62fdcc1127SAntonio Nino Diaz ******************************************************************************/ 63fdcc1127SAntonio Nino Diaz struct tegra_bl31_params { 64fdcc1127SAntonio Nino Diaz param_header_t h; 65fdcc1127SAntonio Nino Diaz image_info_t *bl31_image_info; 66fdcc1127SAntonio Nino Diaz entry_point_info_t *bl32_ep_info; 67fdcc1127SAntonio Nino Diaz image_info_t *bl32_image_info; 68fdcc1127SAntonio Nino Diaz entry_point_info_t *bl33_ep_info; 69fdcc1127SAntonio Nino Diaz image_info_t *bl33_image_info; 70fdcc1127SAntonio Nino Diaz }; 71fdcc1127SAntonio Nino Diaz 7293eafbcaSVarun Wadekar /* Declarations for plat_psci_handlers.c */ 73214e8464SAnthony Zhou int32_t tegra_soc_validate_power_state(uint32_t power_state, 7471cb26eaSVarun Wadekar psci_power_state_t *req_state); 7593eafbcaSVarun Wadekar 7608438e24SVarun Wadekar /* Declarations for plat_setup.c */ 7708438e24SVarun Wadekar const mmap_region_t *plat_get_mmio_map(void); 78d6102295SAnthony Zhou uint32_t plat_get_console_from_id(int32_t id); 79d3360301SVarun Wadekar void plat_gic_setup(void); 80fdcc1127SAntonio Nino Diaz struct tegra_bl31_params *plat_get_bl31_params(void); 818ab06d2fSVarun Wadekar plat_params_from_bl2_t *plat_get_bl31_plat_params(void); 823e1923d9SDilan Lee void plat_early_platform_setup(void); 833e1923d9SDilan Lee void plat_late_platform_setup(void); 8408438e24SVarun Wadekar 8508438e24SVarun Wadekar /* Declarations for plat_secondary.c */ 8608438e24SVarun Wadekar void plat_secondary_setup(void); 87592035d0SAnthony Zhou int32_t plat_lock_cpu_vectors(void); 8808438e24SVarun Wadekar 8978e2bd10SVarun Wadekar /* Declarations for tegra_fiq_glue.c */ 9078e2bd10SVarun Wadekar void tegra_fiq_handler_setup(void); 9178e2bd10SVarun Wadekar int tegra_fiq_get_intr_context(void); 9278e2bd10SVarun Wadekar void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); 9378e2bd10SVarun Wadekar 9408438e24SVarun Wadekar /* Declarations for tegra_security.c */ 9508438e24SVarun Wadekar void tegra_security_setup(void); 9608438e24SVarun Wadekar void tegra_security_setup_videomem(uintptr_t base, uint64_t size); 9708438e24SVarun Wadekar 9808438e24SVarun Wadekar /* Declarations for tegra_pm.c */ 99a9e0260cSVignesh Radhakrishnan extern uint8_t tegra_fake_system_suspend; 100a9e0260cSVignesh Radhakrishnan 10108438e24SVarun Wadekar void tegra_pm_system_suspend_entry(void); 10208438e24SVarun Wadekar void tegra_pm_system_suspend_exit(void); 103b36aea5aSAnthony Zhou int32_t tegra_system_suspended(void); 1040887026eSVarun Wadekar int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state); 105b36aea5aSAnthony Zhou int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state); 106b36aea5aSAnthony Zhou int32_t tegra_soc_pwr_domain_on(u_register_t mpidr); 107b36aea5aSAnthony Zhou int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state); 108b36aea5aSAnthony Zhou int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state); 109b36aea5aSAnthony Zhou int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); 110b36aea5aSAnthony Zhou int32_t tegra_soc_prepare_system_reset(void); 111b36aea5aSAnthony Zhou __dead2 void tegra_soc_prepare_system_off(void); 112b36aea5aSAnthony Zhou plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, 113b36aea5aSAnthony Zhou const plat_local_state_t *states, 114b36aea5aSAnthony Zhou uint32_t ncpu); 115b36aea5aSAnthony Zhou void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state); 116b36aea5aSAnthony Zhou void tegra_cpu_standby(plat_local_state_t cpu_state); 117b36aea5aSAnthony Zhou int32_t tegra_pwr_domain_on(u_register_t mpidr); 118b36aea5aSAnthony Zhou void tegra_pwr_domain_off(const psci_power_state_t *target_state); 119b36aea5aSAnthony Zhou void tegra_pwr_domain_suspend(const psci_power_state_t *target_state); 120b36aea5aSAnthony Zhou void __dead2 tegra_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); 121b36aea5aSAnthony Zhou void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state); 122b36aea5aSAnthony Zhou void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state); 123b36aea5aSAnthony Zhou __dead2 void tegra_system_off(void); 124b36aea5aSAnthony Zhou __dead2 void tegra_system_reset(void); 125b36aea5aSAnthony Zhou int32_t tegra_validate_power_state(uint32_t power_state, 126b36aea5aSAnthony Zhou psci_power_state_t *req_state); 127b36aea5aSAnthony Zhou int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint); 12808438e24SVarun Wadekar 12908438e24SVarun Wadekar /* Declarations for tegraXXX_pm.c */ 13008438e24SVarun Wadekar int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); 13108438e24SVarun Wadekar int tegra_prepare_cpu_on_finish(unsigned long mpidr); 13208438e24SVarun Wadekar 13308438e24SVarun Wadekar /* Declarations for tegra_bl31_setup.c */ 13408438e24SVarun Wadekar plat_params_from_bl2_t *bl31_get_plat_params(void); 135fcf23a14SVarun Wadekar int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); 13608438e24SVarun Wadekar 137c8961326SVarun Wadekar /* Declarations for tegra_delay_timer.c */ 138c8961326SVarun Wadekar void tegra_delay_timer_init(void); 139c8961326SVarun Wadekar 14068c7de6fSVarun Wadekar void tegra_secure_entrypoint(void); 14168c7de6fSVarun Wadekar void tegra186_cpu_reset_handler(void); 14268c7de6fSVarun Wadekar 1431d49112bSAnthony Zhou /* Declarations for tegra_sip_calls.c */ 1441d49112bSAnthony Zhou uintptr_t tegra_sip_handler(uint32_t smc_fid, 1451d49112bSAnthony Zhou u_register_t x1, 1461d49112bSAnthony Zhou u_register_t x2, 1471d49112bSAnthony Zhou u_register_t x3, 1481d49112bSAnthony Zhou u_register_t x4, 1491d49112bSAnthony Zhou void *cookie, 1501d49112bSAnthony Zhou void *handle, 1511d49112bSAnthony Zhou u_register_t flags); 1521d49112bSAnthony Zhou int plat_sip_handler(uint32_t smc_fid, 1531d49112bSAnthony Zhou uint64_t x1, 1541d49112bSAnthony Zhou uint64_t x2, 1551d49112bSAnthony Zhou uint64_t x3, 1561d49112bSAnthony Zhou uint64_t x4, 1571d49112bSAnthony Zhou const void *cookie, 1581d49112bSAnthony Zhou void *handle, 1591d49112bSAnthony Zhou uint64_t flags); 1601d49112bSAnthony Zhou 161c3cf06f1SAntonio Nino Diaz #endif /* TEGRA_PRIVATE_H */ 162