108438e24SVarun Wadekar /* 250e91633SAnthony Zhou * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 708438e24SVarun Wadekar #ifndef __TEGRA_PRIVATE_H__ 808438e24SVarun Wadekar #define __TEGRA_PRIVATE_H__ 908438e24SVarun Wadekar 1071cb26eaSVarun Wadekar #include <arch.h> 1108438e24SVarun Wadekar #include <platform_def.h> 12ca8b7d51SYatharth Kochar #include <psci.h> 13*28db3e96SAndreas Färber #include <xlat_tables_v2.h> 1408438e24SVarun Wadekar 159a964510SVarun Wadekar /******************************************************************************* 169a964510SVarun Wadekar * Tegra DRAM memory base address 179a964510SVarun Wadekar ******************************************************************************/ 1870cb692eSVarun Wadekar #define TEGRA_DRAM_BASE ULL(0x80000000) 1970cb692eSVarun Wadekar #define TEGRA_DRAM_END ULL(0x27FFFFFFF) 209a964510SVarun Wadekar 21d3360301SVarun Wadekar /******************************************************************************* 22d3360301SVarun Wadekar * Struct for parameters received from BL2 23d3360301SVarun Wadekar ******************************************************************************/ 2408438e24SVarun Wadekar typedef struct plat_params_from_bl2 { 25e0d4158cSVarun Wadekar /* TZ memory size */ 2608438e24SVarun Wadekar uint64_t tzdram_size; 27e0d4158cSVarun Wadekar /* TZ memory base */ 28e0d4158cSVarun Wadekar uint64_t tzdram_base; 29e1084216SVarun Wadekar /* UART port ID */ 30e1084216SVarun Wadekar int uart_id; 3108438e24SVarun Wadekar } plat_params_from_bl2_t; 3208438e24SVarun Wadekar 3378e2bd10SVarun Wadekar /******************************************************************************* 3478e2bd10SVarun Wadekar * Per-CPU struct describing FIQ state to be stored 3578e2bd10SVarun Wadekar ******************************************************************************/ 3678e2bd10SVarun Wadekar typedef struct pcpu_fiq_state { 3778e2bd10SVarun Wadekar uint64_t elr_el3; 3878e2bd10SVarun Wadekar uint64_t spsr_el3; 3978e2bd10SVarun Wadekar } pcpu_fiq_state_t; 4078e2bd10SVarun Wadekar 4145eab456SVarun Wadekar /******************************************************************************* 4245eab456SVarun Wadekar * Struct describing per-FIQ configuration settings 4345eab456SVarun Wadekar ******************************************************************************/ 4445eab456SVarun Wadekar typedef struct irq_sec_cfg { 4545eab456SVarun Wadekar /* IRQ number */ 4645eab456SVarun Wadekar unsigned int irq; 4745eab456SVarun Wadekar /* Target CPUs servicing this interrupt */ 4845eab456SVarun Wadekar unsigned int target_cpus; 4945eab456SVarun Wadekar /* type = INTR_TYPE_S_EL1 or INTR_TYPE_EL3 */ 5045eab456SVarun Wadekar uint32_t type; 5145eab456SVarun Wadekar } irq_sec_cfg_t; 5245eab456SVarun Wadekar 5393eafbcaSVarun Wadekar /* Declarations for plat_psci_handlers.c */ 5471cb26eaSVarun Wadekar int32_t tegra_soc_validate_power_state(unsigned int power_state, 5571cb26eaSVarun Wadekar psci_power_state_t *req_state); 5693eafbcaSVarun Wadekar 5708438e24SVarun Wadekar /* Declarations for plat_setup.c */ 5808438e24SVarun Wadekar const mmap_region_t *plat_get_mmio_map(void); 59e1084216SVarun Wadekar uint32_t plat_get_console_from_id(int id); 60d3360301SVarun Wadekar void plat_gic_setup(void); 618ab06d2fSVarun Wadekar bl31_params_t *plat_get_bl31_params(void); 628ab06d2fSVarun Wadekar plat_params_from_bl2_t *plat_get_bl31_plat_params(void); 6308438e24SVarun Wadekar 6408438e24SVarun Wadekar /* Declarations for plat_secondary.c */ 6508438e24SVarun Wadekar void plat_secondary_setup(void); 6608438e24SVarun Wadekar int plat_lock_cpu_vectors(void); 6708438e24SVarun Wadekar 6878e2bd10SVarun Wadekar /* Declarations for tegra_fiq_glue.c */ 6978e2bd10SVarun Wadekar void tegra_fiq_handler_setup(void); 7078e2bd10SVarun Wadekar int tegra_fiq_get_intr_context(void); 7178e2bd10SVarun Wadekar void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); 7278e2bd10SVarun Wadekar 7308438e24SVarun Wadekar /* Declarations for tegra_gic.c */ 7408438e24SVarun Wadekar void tegra_gic_cpuif_deactivate(void); 759a8f05e4SVarun Wadekar void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, uint32_t num_irqs); 7608438e24SVarun Wadekar 7708438e24SVarun Wadekar /* Declarations for tegra_security.c */ 7808438e24SVarun Wadekar void tegra_security_setup(void); 7908438e24SVarun Wadekar void tegra_security_setup_videomem(uintptr_t base, uint64_t size); 8008438e24SVarun Wadekar 8108438e24SVarun Wadekar /* Declarations for tegra_pm.c */ 82a9e0260cSVignesh Radhakrishnan extern uint8_t tegra_fake_system_suspend; 83a9e0260cSVignesh Radhakrishnan 8408438e24SVarun Wadekar void tegra_pm_system_suspend_entry(void); 8508438e24SVarun Wadekar void tegra_pm_system_suspend_exit(void); 8608438e24SVarun Wadekar int tegra_system_suspended(void); 8708438e24SVarun Wadekar 8808438e24SVarun Wadekar /* Declarations for tegraXXX_pm.c */ 8908438e24SVarun Wadekar int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); 9008438e24SVarun Wadekar int tegra_prepare_cpu_on_finish(unsigned long mpidr); 9108438e24SVarun Wadekar 9208438e24SVarun Wadekar /* Declarations for tegra_bl31_setup.c */ 9308438e24SVarun Wadekar plat_params_from_bl2_t *bl31_get_plat_params(void); 949a964510SVarun Wadekar int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); 955ea0b028SVarun Wadekar void plat_early_platform_setup(void); 9608438e24SVarun Wadekar 97c8961326SVarun Wadekar /* Declarations for tegra_delay_timer.c */ 98c8961326SVarun Wadekar void tegra_delay_timer_init(void); 99c8961326SVarun Wadekar 10068c7de6fSVarun Wadekar void tegra_secure_entrypoint(void); 10168c7de6fSVarun Wadekar void tegra186_cpu_reset_handler(void); 10268c7de6fSVarun Wadekar 10308438e24SVarun Wadekar #endif /* __TEGRA_PRIVATE_H__ */ 104