108438e24SVarun Wadekar /* 250e91633SAnthony Zhou * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 7c3cf06f1SAntonio Nino Diaz #ifndef TEGRA_PRIVATE_H 8c3cf06f1SAntonio Nino Diaz #define TEGRA_PRIVATE_H 908438e24SVarun Wadekar 1009d40e0eSAntonio Nino Diaz #include <platform_def.h> 1109d40e0eSAntonio Nino Diaz 1271cb26eaSVarun Wadekar #include <arch.h> 1380c50eeaSVarun Wadekar #include <arch_helpers.h> 1409d40e0eSAntonio Nino Diaz #include <lib/psci/psci.h> 1509d40e0eSAntonio Nino Diaz #include <lib/xlat_tables/xlat_tables_v2.h> 1609d40e0eSAntonio Nino Diaz 1780c50eeaSVarun Wadekar #include <tegra_gic.h> 1808438e24SVarun Wadekar 199a964510SVarun Wadekar /******************************************************************************* 209a964510SVarun Wadekar * Tegra DRAM memory base address 219a964510SVarun Wadekar ******************************************************************************/ 2270cb692eSVarun Wadekar #define TEGRA_DRAM_BASE ULL(0x80000000) 2370cb692eSVarun Wadekar #define TEGRA_DRAM_END ULL(0x27FFFFFFF) 249a964510SVarun Wadekar 25d3360301SVarun Wadekar /******************************************************************************* 26d3360301SVarun Wadekar * Struct for parameters received from BL2 27d3360301SVarun Wadekar ******************************************************************************/ 2808438e24SVarun Wadekar typedef struct plat_params_from_bl2 { 29e0d4158cSVarun Wadekar /* TZ memory size */ 3008438e24SVarun Wadekar uint64_t tzdram_size; 31e0d4158cSVarun Wadekar /* TZ memory base */ 32e0d4158cSVarun Wadekar uint64_t tzdram_base; 33e1084216SVarun Wadekar /* UART port ID */ 34e1084216SVarun Wadekar int uart_id; 35b495791bSHarvey Hsieh /* L2 ECC parity protection disable flag */ 36b495791bSHarvey Hsieh int l2_ecc_parity_prot_dis; 3708438e24SVarun Wadekar } plat_params_from_bl2_t; 3808438e24SVarun Wadekar 3978e2bd10SVarun Wadekar /******************************************************************************* 40b495791bSHarvey Hsieh * Helper function to access l2ctlr_el1 register on Cortex-A57 CPUs 41b495791bSHarvey Hsieh ******************************************************************************/ 42b495791bSHarvey Hsieh DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1) 43b495791bSHarvey Hsieh 44b495791bSHarvey Hsieh /******************************************************************************* 45fdcc1127SAntonio Nino Diaz * Struct describing parameters passed to bl31 46fdcc1127SAntonio Nino Diaz ******************************************************************************/ 47fdcc1127SAntonio Nino Diaz struct tegra_bl31_params { 48fdcc1127SAntonio Nino Diaz param_header_t h; 49fdcc1127SAntonio Nino Diaz image_info_t *bl31_image_info; 50fdcc1127SAntonio Nino Diaz entry_point_info_t *bl32_ep_info; 51fdcc1127SAntonio Nino Diaz image_info_t *bl32_image_info; 52fdcc1127SAntonio Nino Diaz entry_point_info_t *bl33_ep_info; 53fdcc1127SAntonio Nino Diaz image_info_t *bl33_image_info; 54fdcc1127SAntonio Nino Diaz }; 55fdcc1127SAntonio Nino Diaz 5693eafbcaSVarun Wadekar /* Declarations for plat_psci_handlers.c */ 5771cb26eaSVarun Wadekar int32_t tegra_soc_validate_power_state(unsigned int power_state, 5871cb26eaSVarun Wadekar psci_power_state_t *req_state); 5993eafbcaSVarun Wadekar 6008438e24SVarun Wadekar /* Declarations for plat_setup.c */ 6108438e24SVarun Wadekar const mmap_region_t *plat_get_mmio_map(void); 62e1084216SVarun Wadekar uint32_t plat_get_console_from_id(int id); 63d3360301SVarun Wadekar void plat_gic_setup(void); 64fdcc1127SAntonio Nino Diaz struct tegra_bl31_params *plat_get_bl31_params(void); 658ab06d2fSVarun Wadekar plat_params_from_bl2_t *plat_get_bl31_plat_params(void); 6608438e24SVarun Wadekar 6708438e24SVarun Wadekar /* Declarations for plat_secondary.c */ 6808438e24SVarun Wadekar void plat_secondary_setup(void); 6908438e24SVarun Wadekar int plat_lock_cpu_vectors(void); 7008438e24SVarun Wadekar 7178e2bd10SVarun Wadekar /* Declarations for tegra_fiq_glue.c */ 7278e2bd10SVarun Wadekar void tegra_fiq_handler_setup(void); 7378e2bd10SVarun Wadekar int tegra_fiq_get_intr_context(void); 7478e2bd10SVarun Wadekar void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); 7578e2bd10SVarun Wadekar 7608438e24SVarun Wadekar /* Declarations for tegra_security.c */ 7708438e24SVarun Wadekar void tegra_security_setup(void); 7808438e24SVarun Wadekar void tegra_security_setup_videomem(uintptr_t base, uint64_t size); 7908438e24SVarun Wadekar 8008438e24SVarun Wadekar /* Declarations for tegra_pm.c */ 81a9e0260cSVignesh Radhakrishnan extern uint8_t tegra_fake_system_suspend; 82a9e0260cSVignesh Radhakrishnan 8308438e24SVarun Wadekar void tegra_pm_system_suspend_entry(void); 8408438e24SVarun Wadekar void tegra_pm_system_suspend_exit(void); 8508438e24SVarun Wadekar int tegra_system_suspended(void); 8608438e24SVarun Wadekar 8708438e24SVarun Wadekar /* Declarations for tegraXXX_pm.c */ 8808438e24SVarun Wadekar int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); 8908438e24SVarun Wadekar int tegra_prepare_cpu_on_finish(unsigned long mpidr); 9008438e24SVarun Wadekar 9108438e24SVarun Wadekar /* Declarations for tegra_bl31_setup.c */ 9208438e24SVarun Wadekar plat_params_from_bl2_t *bl31_get_plat_params(void); 939a964510SVarun Wadekar int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); 945ea0b028SVarun Wadekar void plat_early_platform_setup(void); 9508438e24SVarun Wadekar 96c8961326SVarun Wadekar /* Declarations for tegra_delay_timer.c */ 97c8961326SVarun Wadekar void tegra_delay_timer_init(void); 98c8961326SVarun Wadekar 9968c7de6fSVarun Wadekar void tegra_secure_entrypoint(void); 10068c7de6fSVarun Wadekar void tegra186_cpu_reset_handler(void); 10168c7de6fSVarun Wadekar 102*1d49112bSAnthony Zhou /* Declarations for tegra_sip_calls.c */ 103*1d49112bSAnthony Zhou uintptr_t tegra_sip_handler(uint32_t smc_fid, 104*1d49112bSAnthony Zhou u_register_t x1, 105*1d49112bSAnthony Zhou u_register_t x2, 106*1d49112bSAnthony Zhou u_register_t x3, 107*1d49112bSAnthony Zhou u_register_t x4, 108*1d49112bSAnthony Zhou void *cookie, 109*1d49112bSAnthony Zhou void *handle, 110*1d49112bSAnthony Zhou u_register_t flags); 111*1d49112bSAnthony Zhou int plat_sip_handler(uint32_t smc_fid, 112*1d49112bSAnthony Zhou uint64_t x1, 113*1d49112bSAnthony Zhou uint64_t x2, 114*1d49112bSAnthony Zhou uint64_t x3, 115*1d49112bSAnthony Zhou uint64_t x4, 116*1d49112bSAnthony Zhou const void *cookie, 117*1d49112bSAnthony Zhou void *handle, 118*1d49112bSAnthony Zhou uint64_t flags); 119*1d49112bSAnthony Zhou 120c3cf06f1SAntonio Nino Diaz #endif /* TEGRA_PRIVATE_H */ 121