108438e24SVarun Wadekar /* 250e91633SAnthony Zhou * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 7c3cf06f1SAntonio Nino Diaz #ifndef TEGRA_PRIVATE_H 8c3cf06f1SAntonio Nino Diaz #define TEGRA_PRIVATE_H 908438e24SVarun Wadekar 10*09d40e0eSAntonio Nino Diaz #include <platform_def.h> 11*09d40e0eSAntonio Nino Diaz 1271cb26eaSVarun Wadekar #include <arch.h> 1380c50eeaSVarun Wadekar #include <arch_helpers.h> 14*09d40e0eSAntonio Nino Diaz #include <lib/psci/psci.h> 15*09d40e0eSAntonio Nino Diaz #include <lib/xlat_tables/xlat_tables_v2.h> 16*09d40e0eSAntonio Nino Diaz 1780c50eeaSVarun Wadekar #include <tegra_gic.h> 1808438e24SVarun Wadekar 199a964510SVarun Wadekar /******************************************************************************* 209a964510SVarun Wadekar * Tegra DRAM memory base address 219a964510SVarun Wadekar ******************************************************************************/ 2270cb692eSVarun Wadekar #define TEGRA_DRAM_BASE ULL(0x80000000) 2370cb692eSVarun Wadekar #define TEGRA_DRAM_END ULL(0x27FFFFFFF) 249a964510SVarun Wadekar 25d3360301SVarun Wadekar /******************************************************************************* 26d3360301SVarun Wadekar * Struct for parameters received from BL2 27d3360301SVarun Wadekar ******************************************************************************/ 2808438e24SVarun Wadekar typedef struct plat_params_from_bl2 { 29e0d4158cSVarun Wadekar /* TZ memory size */ 3008438e24SVarun Wadekar uint64_t tzdram_size; 31e0d4158cSVarun Wadekar /* TZ memory base */ 32e0d4158cSVarun Wadekar uint64_t tzdram_base; 33e1084216SVarun Wadekar /* UART port ID */ 34e1084216SVarun Wadekar int uart_id; 3508438e24SVarun Wadekar } plat_params_from_bl2_t; 3608438e24SVarun Wadekar 3778e2bd10SVarun Wadekar /******************************************************************************* 38fdcc1127SAntonio Nino Diaz * Struct describing parameters passed to bl31 39fdcc1127SAntonio Nino Diaz ******************************************************************************/ 40fdcc1127SAntonio Nino Diaz struct tegra_bl31_params { 41fdcc1127SAntonio Nino Diaz param_header_t h; 42fdcc1127SAntonio Nino Diaz image_info_t *bl31_image_info; 43fdcc1127SAntonio Nino Diaz entry_point_info_t *bl32_ep_info; 44fdcc1127SAntonio Nino Diaz image_info_t *bl32_image_info; 45fdcc1127SAntonio Nino Diaz entry_point_info_t *bl33_ep_info; 46fdcc1127SAntonio Nino Diaz image_info_t *bl33_image_info; 47fdcc1127SAntonio Nino Diaz }; 48fdcc1127SAntonio Nino Diaz 4993eafbcaSVarun Wadekar /* Declarations for plat_psci_handlers.c */ 5071cb26eaSVarun Wadekar int32_t tegra_soc_validate_power_state(unsigned int power_state, 5171cb26eaSVarun Wadekar psci_power_state_t *req_state); 5293eafbcaSVarun Wadekar 5308438e24SVarun Wadekar /* Declarations for plat_setup.c */ 5408438e24SVarun Wadekar const mmap_region_t *plat_get_mmio_map(void); 55e1084216SVarun Wadekar uint32_t plat_get_console_from_id(int id); 56d3360301SVarun Wadekar void plat_gic_setup(void); 57fdcc1127SAntonio Nino Diaz struct tegra_bl31_params *plat_get_bl31_params(void); 588ab06d2fSVarun Wadekar plat_params_from_bl2_t *plat_get_bl31_plat_params(void); 5908438e24SVarun Wadekar 6008438e24SVarun Wadekar /* Declarations for plat_secondary.c */ 6108438e24SVarun Wadekar void plat_secondary_setup(void); 6208438e24SVarun Wadekar int plat_lock_cpu_vectors(void); 6308438e24SVarun Wadekar 6478e2bd10SVarun Wadekar /* Declarations for tegra_fiq_glue.c */ 6578e2bd10SVarun Wadekar void tegra_fiq_handler_setup(void); 6678e2bd10SVarun Wadekar int tegra_fiq_get_intr_context(void); 6778e2bd10SVarun Wadekar void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); 6878e2bd10SVarun Wadekar 6908438e24SVarun Wadekar /* Declarations for tegra_security.c */ 7008438e24SVarun Wadekar void tegra_security_setup(void); 7108438e24SVarun Wadekar void tegra_security_setup_videomem(uintptr_t base, uint64_t size); 7208438e24SVarun Wadekar 7308438e24SVarun Wadekar /* Declarations for tegra_pm.c */ 74a9e0260cSVignesh Radhakrishnan extern uint8_t tegra_fake_system_suspend; 75a9e0260cSVignesh Radhakrishnan 7608438e24SVarun Wadekar void tegra_pm_system_suspend_entry(void); 7708438e24SVarun Wadekar void tegra_pm_system_suspend_exit(void); 7808438e24SVarun Wadekar int tegra_system_suspended(void); 7908438e24SVarun Wadekar 8008438e24SVarun Wadekar /* Declarations for tegraXXX_pm.c */ 8108438e24SVarun Wadekar int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); 8208438e24SVarun Wadekar int tegra_prepare_cpu_on_finish(unsigned long mpidr); 8308438e24SVarun Wadekar 8408438e24SVarun Wadekar /* Declarations for tegra_bl31_setup.c */ 8508438e24SVarun Wadekar plat_params_from_bl2_t *bl31_get_plat_params(void); 869a964510SVarun Wadekar int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); 875ea0b028SVarun Wadekar void plat_early_platform_setup(void); 8808438e24SVarun Wadekar 89c8961326SVarun Wadekar /* Declarations for tegra_delay_timer.c */ 90c8961326SVarun Wadekar void tegra_delay_timer_init(void); 91c8961326SVarun Wadekar 9268c7de6fSVarun Wadekar void tegra_secure_entrypoint(void); 9368c7de6fSVarun Wadekar void tegra186_cpu_reset_handler(void); 9468c7de6fSVarun Wadekar 95c3cf06f1SAntonio Nino Diaz #endif /* TEGRA_PRIVATE_H */ 96