1e954ab8fSVarun Wadekar /* 293c78ed2SAntonio Nino Diaz * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3e954ab8fSVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5e954ab8fSVarun Wadekar */ 6e954ab8fSVarun Wadekar 7c3cf06f1SAntonio Nino Diaz #ifndef TEGRA_PLATFORM_H 8c3cf06f1SAntonio Nino Diaz #define TEGRA_PLATFORM_H 9e954ab8fSVarun Wadekar 1093c78ed2SAntonio Nino Diaz #include <cdefs.h> 116e756f6dSAmbroise Vincent #include <lib/utils_def.h> 12c62be079SAnthony Zhou #include <stdbool.h> 13d3b71331SMarvin Hsu 14d3b71331SMarvin Hsu /******************************************************************************* 15d3b71331SMarvin Hsu * Tegra major, minor version helper macros 16d3b71331SMarvin Hsu ******************************************************************************/ 17d3b71331SMarvin Hsu #define MAJOR_VERSION_SHIFT U(0x4) 18d3b71331SMarvin Hsu #define MAJOR_VERSION_MASK U(0xF) 19d3b71331SMarvin Hsu #define MINOR_VERSION_SHIFT U(0x10) 20d3b71331SMarvin Hsu #define MINOR_VERSION_MASK U(0xF) 21d3b71331SMarvin Hsu #define CHIP_ID_SHIFT U(8) 22d3b71331SMarvin Hsu #define CHIP_ID_MASK U(0xFF) 23d3b71331SMarvin Hsu #define PRE_SI_PLATFORM_SHIFT U(0x14) 24d3b71331SMarvin Hsu #define PRE_SI_PLATFORM_MASK U(0xF) 25e954ab8fSVarun Wadekar 26c195fec6SHarvey Hsieh /******************************************************************************* 27d3b71331SMarvin Hsu * Tegra chip ID values 28c195fec6SHarvey Hsieh ******************************************************************************/ 29c195fec6SHarvey Hsieh #define TEGRA_CHIPID_TEGRA13 U(0x13) 30c195fec6SHarvey Hsieh #define TEGRA_CHIPID_TEGRA21 U(0x21) 31c195fec6SHarvey Hsieh #define TEGRA_CHIPID_TEGRA18 U(0x18) 32c195fec6SHarvey Hsieh 33*d5dfdeb6SJulius Werner #ifndef __ASSEMBLER__ 34c195fec6SHarvey Hsieh 35c195fec6SHarvey Hsieh /* 36c195fec6SHarvey Hsieh * Tegra chip ID major/minor identifiers 37ea6dec5dSVarun Wadekar */ 38ea6dec5dSVarun Wadekar uint32_t tegra_get_chipid_major(void); 39ea6dec5dSVarun Wadekar uint32_t tegra_get_chipid_minor(void); 40ea6dec5dSVarun Wadekar 41ea6dec5dSVarun Wadekar /* 42d3b71331SMarvin Hsu * Tegra chip ID identifiers 43e954ab8fSVarun Wadekar */ 44d3b71331SMarvin Hsu bool tegra_chipid_is_t132(void); 45d3b71331SMarvin Hsu bool tegra_chipid_is_t186(void); 46d3b71331SMarvin Hsu bool tegra_chipid_is_t210(void); 47d3b71331SMarvin Hsu bool tegra_chipid_is_t210_b01(void); 48cd3de432SVarun Wadekar 49e954ab8fSVarun Wadekar /* 50e954ab8fSVarun Wadekar * Tegra platform identifiers 51e954ab8fSVarun Wadekar */ 52c62be079SAnthony Zhou bool tegra_platform_is_silicon(void); 53c62be079SAnthony Zhou bool tegra_platform_is_qt(void); 54c62be079SAnthony Zhou bool tegra_platform_is_emulation(void); 55c62be079SAnthony Zhou bool tegra_platform_is_linsim(void); 56c62be079SAnthony Zhou bool tegra_platform_is_fpga(void); 57c62be079SAnthony Zhou bool tegra_platform_is_unit_fpga(void); 58c62be079SAnthony Zhou bool tegra_platform_is_virt_dev_kit(void); 59e954ab8fSVarun Wadekar 60*d5dfdeb6SJulius Werner #endif /* __ASSEMBLER__ */ 61c195fec6SHarvey Hsieh 62c3cf06f1SAntonio Nino Diaz #endif /* TEGRA_PLATFORM_H */ 63