1e954ab8fSVarun Wadekar /* 293c78ed2SAntonio Nino Diaz * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*d4ad3da0SVarun Wadekar * Copyright (c) 2020-2021, NVIDIA Corporation. All rights reserved. 4e954ab8fSVarun Wadekar * 582cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 6e954ab8fSVarun Wadekar */ 7e954ab8fSVarun Wadekar 8c3cf06f1SAntonio Nino Diaz #ifndef TEGRA_PLATFORM_H 9c3cf06f1SAntonio Nino Diaz #define TEGRA_PLATFORM_H 10e954ab8fSVarun Wadekar 1193c78ed2SAntonio Nino Diaz #include <cdefs.h> 126e756f6dSAmbroise Vincent #include <lib/utils_def.h> 13c62be079SAnthony Zhou #include <stdbool.h> 14d3b71331SMarvin Hsu 15d3b71331SMarvin Hsu /******************************************************************************* 16d3b71331SMarvin Hsu * Tegra major, minor version helper macros 17d3b71331SMarvin Hsu ******************************************************************************/ 18d3b71331SMarvin Hsu #define MAJOR_VERSION_SHIFT U(0x4) 19d3b71331SMarvin Hsu #define MAJOR_VERSION_MASK U(0xF) 20d3b71331SMarvin Hsu #define MINOR_VERSION_SHIFT U(0x10) 21d3b71331SMarvin Hsu #define MINOR_VERSION_MASK U(0xF) 22d3b71331SMarvin Hsu #define CHIP_ID_SHIFT U(8) 23d3b71331SMarvin Hsu #define CHIP_ID_MASK U(0xFF) 24d3b71331SMarvin Hsu #define PRE_SI_PLATFORM_SHIFT U(0x14) 25d3b71331SMarvin Hsu #define PRE_SI_PLATFORM_MASK U(0xF) 26e954ab8fSVarun Wadekar 27c195fec6SHarvey Hsieh /******************************************************************************* 28d3b71331SMarvin Hsu * Tegra chip ID values 29c195fec6SHarvey Hsieh ******************************************************************************/ 30c195fec6SHarvey Hsieh #define TEGRA_CHIPID_TEGRA13 U(0x13) 31c195fec6SHarvey Hsieh #define TEGRA_CHIPID_TEGRA21 U(0x21) 32c195fec6SHarvey Hsieh #define TEGRA_CHIPID_TEGRA18 U(0x18) 3343d22073SDavid Pu #define TEGRA_CHIPID_TEGRA19 U(0x19) 34c195fec6SHarvey Hsieh 35b5b2923dSVarun Wadekar /******************************************************************************* 36b5b2923dSVarun Wadekar * JEDEC Standard Manufacturer's Identification Code and Bank ID 37b5b2923dSVarun Wadekar ******************************************************************************/ 38b5b2923dSVarun Wadekar #define JEDEC_NVIDIA_MFID U(0x6B) 39b5b2923dSVarun Wadekar #define JEDEC_NVIDIA_BKID U(3) 40b5b2923dSVarun Wadekar 41d5dfdeb6SJulius Werner #ifndef __ASSEMBLER__ 42c195fec6SHarvey Hsieh 43c195fec6SHarvey Hsieh /* 44c195fec6SHarvey Hsieh * Tegra chip ID major/minor identifiers 45ea6dec5dSVarun Wadekar */ 46ea6dec5dSVarun Wadekar uint32_t tegra_get_chipid_major(void); 47ea6dec5dSVarun Wadekar uint32_t tegra_get_chipid_minor(void); 48ea6dec5dSVarun Wadekar 49ea6dec5dSVarun Wadekar /* 50d3b71331SMarvin Hsu * Tegra chip ID identifiers 51e954ab8fSVarun Wadekar */ 52d3b71331SMarvin Hsu bool tegra_chipid_is_t186(void); 53d3b71331SMarvin Hsu bool tegra_chipid_is_t210(void); 54d3b71331SMarvin Hsu bool tegra_chipid_is_t210_b01(void); 5543d22073SDavid Pu bool tegra_chipid_is_t194(void); 56cd3de432SVarun Wadekar 57e954ab8fSVarun Wadekar /* 58e954ab8fSVarun Wadekar * Tegra platform identifiers 59e954ab8fSVarun Wadekar */ 60c62be079SAnthony Zhou bool tegra_platform_is_silicon(void); 61c62be079SAnthony Zhou bool tegra_platform_is_qt(void); 62c62be079SAnthony Zhou bool tegra_platform_is_emulation(void); 63c62be079SAnthony Zhou bool tegra_platform_is_linsim(void); 64c62be079SAnthony Zhou bool tegra_platform_is_fpga(void); 65c62be079SAnthony Zhou bool tegra_platform_is_unit_fpga(void); 66c62be079SAnthony Zhou bool tegra_platform_is_virt_dev_kit(void); 67e954ab8fSVarun Wadekar 68d5dfdeb6SJulius Werner #endif /* __ASSEMBLER__ */ 69c195fec6SHarvey Hsieh 70c3cf06f1SAntonio Nino Diaz #endif /* TEGRA_PLATFORM_H */ 71