1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TEGRA_DEF_H 8 #define TEGRA_DEF_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * Power down state IDs 14 ******************************************************************************/ 15 #define PSTATE_ID_CORE_POWERDN U(7) 16 #define PSTATE_ID_CLUSTER_IDLE U(16) 17 #define PSTATE_ID_CLUSTER_POWERDN U(17) 18 #define PSTATE_ID_SOC_POWERDN U(27) 19 20 /******************************************************************************* 21 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 22 * call as the `state-id` field in the 'power state' parameter. 23 ******************************************************************************/ 24 #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN 25 26 /******************************************************************************* 27 * Platform power states (used by PSCI framework) 28 * 29 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 30 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 31 ******************************************************************************/ 32 #define PLAT_MAX_RET_STATE U(1) 33 #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) 34 35 /******************************************************************************* 36 * iRAM memory constants 37 ******************************************************************************/ 38 #define TEGRA_IRAM_BASE 0x40000000 39 40 /******************************************************************************* 41 * GIC memory map 42 ******************************************************************************/ 43 #define TEGRA_GICD_BASE U(0x50041000) 44 #define TEGRA_GICC_BASE U(0x50042000) 45 46 /******************************************************************************* 47 * Tegra Memory Select Switch Controller constants 48 ******************************************************************************/ 49 #define TEGRA_MSELECT_BASE U(0x50060000) 50 51 #define MSELECT_CONFIG U(0x0) 52 #define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29)) 53 #define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28)) 54 #define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27)) 55 #define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25)) 56 #define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24)) 57 #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ 58 UNSUPPORTED_TX_ERR_MASTER1_BIT) 59 #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ 60 ENABLE_WRAP_INCR_MASTER1_BIT | \ 61 ENABLE_WRAP_INCR_MASTER0_BIT) 62 63 /******************************************************************************* 64 * Tegra Resource Semaphore constants 65 ******************************************************************************/ 66 #define TEGRA_RES_SEMA_BASE 0x60001000UL 67 #define STA_OFFSET 0UL 68 #define SET_OFFSET 4UL 69 #define CLR_OFFSET 8UL 70 71 /******************************************************************************* 72 * Tegra Primary Interrupt Controller constants 73 ******************************************************************************/ 74 #define TEGRA_PRI_ICTLR_BASE 0x60004000UL 75 #define CPU_IEP_FIR_SET 0x18UL 76 77 /******************************************************************************* 78 * Tegra micro-seconds timer constants 79 ******************************************************************************/ 80 #define TEGRA_TMRUS_BASE U(0x60005010) 81 #define TEGRA_TMRUS_SIZE U(0x1000) 82 83 /******************************************************************************* 84 * Tegra Clock and Reset Controller constants 85 ******************************************************************************/ 86 #define TEGRA_CAR_RESET_BASE U(0x60006000) 87 #define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) 88 #define GPU_RESET_BIT (U(1) << 24) 89 #define TEGRA_RST_DEV_CLR_V U(0x434) 90 #define TEGRA_CLK_ENB_V U(0x440) 91 92 /******************************************************************************* 93 * Tegra Flow Controller constants 94 ******************************************************************************/ 95 #define TEGRA_FLOWCTRL_BASE U(0x60007000) 96 97 /******************************************************************************* 98 * Tegra AHB arbitration controller 99 ******************************************************************************/ 100 #define TEGRA_AHB_ARB_BASE 0x6000C000UL 101 102 /******************************************************************************* 103 * Tegra Secure Boot Controller constants 104 ******************************************************************************/ 105 #define TEGRA_SB_BASE U(0x6000C200) 106 107 /******************************************************************************* 108 * Tegra Exception Vectors constants 109 ******************************************************************************/ 110 #define TEGRA_EVP_BASE U(0x6000F000) 111 112 /******************************************************************************* 113 * Tegra Miscellaneous register constants 114 ******************************************************************************/ 115 #define TEGRA_MISC_BASE U(0x70000000) 116 #define HARDWARE_REVISION_OFFSET U(0x804) 117 118 /******************************************************************************* 119 * Tegra UART controller base addresses 120 ******************************************************************************/ 121 #define TEGRA_UARTA_BASE U(0x70006000) 122 #define TEGRA_UARTB_BASE U(0x70006040) 123 #define TEGRA_UARTC_BASE U(0x70006200) 124 #define TEGRA_UARTD_BASE U(0x70006300) 125 #define TEGRA_UARTE_BASE U(0x70006400) 126 127 /******************************************************************************* 128 * Tegra Power Mgmt Controller constants 129 ******************************************************************************/ 130 #define TEGRA_PMC_BASE U(0x7000E400) 131 132 /******************************************************************************* 133 * Tegra Atomics constants 134 ******************************************************************************/ 135 #define TEGRA_ATOMICS_BASE 0x70016000UL 136 #define TRIGGER0_REG_OFFSET 0UL 137 #define TRIGGER_WIDTH_SHIFT 4UL 138 #define TRIGGER_ID_SHIFT 16UL 139 #define RESULT0_REG_OFFSET 0xC00UL 140 141 /******************************************************************************* 142 * Tegra Memory Controller constants 143 ******************************************************************************/ 144 #define TEGRA_MC_BASE U(0x70019000) 145 146 /* TZDRAM carveout configuration registers */ 147 #define MC_SECURITY_CFG0_0 U(0x70) 148 #define MC_SECURITY_CFG1_0 U(0x74) 149 #define MC_SECURITY_CFG3_0 U(0x9BC) 150 151 /* Video Memory carveout configuration registers */ 152 #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 153 #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 154 #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) 155 156 /******************************************************************************* 157 * Tegra SE constants 158 ******************************************************************************/ 159 #define TEGRA_SE1_BASE U(0x70012000) 160 #define TEGRA_SE2_BASE U(0x70412000) 161 #define TEGRA_PKA1_BASE U(0x70420000) 162 #define TEGRA_SE2_RANGE_SIZE U(0x2000) 163 #define SE_TZRAM_SECURITY U(0x4) 164 165 /******************************************************************************* 166 * Tegra TZRAM constants 167 ******************************************************************************/ 168 #define TEGRA_TZRAM_BASE U(0x7C010000) 169 #define TEGRA_TZRAM_SIZE U(0x10000) 170 171 #endif /* TEGRA_DEF_H */ 172