1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef TEGRA_DEF_H 9 #define TEGRA_DEF_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * Power down state IDs 15 ******************************************************************************/ 16 #define PSTATE_ID_CORE_POWERDN U(7) 17 #define PSTATE_ID_CLUSTER_IDLE U(16) 18 #define PSTATE_ID_SOC_POWERDN U(27) 19 20 /******************************************************************************* 21 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 22 * call as the `state-id` field in the 'power state' parameter. 23 ******************************************************************************/ 24 #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN 25 26 /******************************************************************************* 27 * Platform power states (used by PSCI framework) 28 * 29 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 30 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 31 ******************************************************************************/ 32 #define PLAT_MAX_RET_STATE U(1) 33 #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) 34 35 /******************************************************************************* 36 * Chip specific page table and MMU setup constants 37 ******************************************************************************/ 38 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) 39 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) 40 41 /******************************************************************************* 42 * SC7 entry firmware's header size 43 ******************************************************************************/ 44 #define SC7ENTRY_FW_HEADER_SIZE_BYTES U(0x400) 45 46 /******************************************************************************* 47 * iRAM memory constants 48 ******************************************************************************/ 49 #define TEGRA_IRAM_BASE U(0x40000000) 50 #define TEGRA_IRAM_A_SIZE U(0x10000) /* 64KB */ 51 #define TEGRA_IRAM_SIZE U(40000) /* 256KB */ 52 53 /******************************************************************************* 54 * GIC memory map 55 ******************************************************************************/ 56 #define TEGRA_GICD_BASE U(0x50041000) 57 #define TEGRA_GICC_BASE U(0x50042000) 58 59 /******************************************************************************* 60 * Secure IRQ definitions 61 ******************************************************************************/ 62 #define TEGRA210_WDT_CPU_LEGACY_FIQ U(28) 63 64 /******************************************************************************* 65 * Tegra Memory Select Switch Controller constants 66 ******************************************************************************/ 67 #define TEGRA_MSELECT_BASE U(0x50060000) 68 69 #define MSELECT_CONFIG U(0x0) 70 #define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29)) 71 #define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28)) 72 #define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27)) 73 #define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25)) 74 #define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24)) 75 #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ 76 UNSUPPORTED_TX_ERR_MASTER1_BIT) 77 #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ 78 ENABLE_WRAP_INCR_MASTER1_BIT | \ 79 ENABLE_WRAP_INCR_MASTER0_BIT) 80 81 /******************************************************************************* 82 * Tegra Resource Semaphore constants 83 ******************************************************************************/ 84 #define TEGRA_RES_SEMA_BASE 0x60001000UL 85 #define STA_OFFSET 0UL 86 #define SET_OFFSET 4UL 87 #define CLR_OFFSET 8UL 88 89 /******************************************************************************* 90 * Tegra Primary Interrupt Controller constants 91 ******************************************************************************/ 92 #define TEGRA_PRI_ICTLR_BASE 0x60004000UL 93 #define CPU_IEP_FIR_SET 0x18UL 94 95 /******************************************************************************* 96 * Tegra micro-seconds timer constants 97 ******************************************************************************/ 98 #define TEGRA_TMRUS_BASE U(0x60005010) 99 #define TEGRA_TMRUS_SIZE U(0x1000) 100 101 /******************************************************************************* 102 * Tegra Clock and Reset Controller constants 103 ******************************************************************************/ 104 #define TEGRA_CAR_RESET_BASE U(0x60006000) 105 #define TEGRA_BOND_OUT_H U(0x74) 106 #define APB_DMA_LOCK_BIT (U(1) << 2) 107 #define AHB_DMA_LOCK_BIT (U(1) << 1) 108 #define TEGRA_BOND_OUT_U U(0x78) 109 #define IRAM_D_LOCK_BIT (U(1) << 23) 110 #define IRAM_C_LOCK_BIT (U(1) << 22) 111 #define IRAM_B_LOCK_BIT (U(1) << 21) 112 #define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) 113 #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290) 114 #define GPU_RESET_BIT (U(1) << 24) 115 #define GPU_SET_BIT (U(1) << 24) 116 #define TEGRA_RST_DEV_SET_Y U(0x2a8) 117 #define NVENC_RESET_BIT (U(1) << 27) 118 #define TSECB_RESET_BIT (U(1) << 14) 119 #define APE_RESET_BIT (U(1) << 6) 120 #define NVJPG_RESET_BIT (U(1) << 3) 121 #define NVDEC_RESET_BIT (U(1) << 2) 122 #define TEGRA_RST_DEV_SET_L U(0x300) 123 #define HOST1X_RESET_BIT (U(1) << 28) 124 #define ISP_RESET_BIT (U(1) << 23) 125 #define USBD_RESET_BIT (U(1) << 22) 126 #define VI_RESET_BIT (U(1) << 20) 127 #define SDMMC4_RESET_BIT (U(1) << 15) 128 #define SDMMC1_RESET_BIT (U(1) << 14) 129 #define SDMMC2_RESET_BIT (U(1) << 9) 130 #define TEGRA_RST_DEV_SET_H U(0x308) 131 #define USB2_RESET_BIT (U(1) << 26) 132 #define APBDMA_RESET_BIT (U(1) << 2) 133 #define AHBDMA_RESET_BIT (U(1) << 1) 134 #define TEGRA_RST_DEV_SET_U U(0x310) 135 #define XUSB_DEV_RESET_BIT (U(1) << 31) 136 #define XUSB_HOST_RESET_BIT (U(1) << 25) 137 #define TSEC_RESET_BIT (U(1) << 19) 138 #define PCIE_RESET_BIT (U(1) << 6) 139 #define SDMMC3_RESET_BIT (U(1) << 5) 140 #define TEGRA_RST_DEVICES_V U(0x358) 141 #define TEGRA_RST_DEVICES_W U(0x35C) 142 #define ENTROPY_CLK_ENB_BIT (U(1) << 21) 143 #define TEGRA_CLK_OUT_ENB_V U(0x360) 144 #define SE_CLK_ENB_BIT (U(1) << 31) 145 #define TEGRA_CLK_OUT_ENB_W U(0x364) 146 #define ENTROPY_RESET_BIT (U(1) << 21) 147 #define TEGRA_RST_DEV_SET_V U(0x430) 148 #define SE_RESET_BIT (U(1) << 31) 149 #define HDA_RESET_BIT (U(1) << 29) 150 #define SATA_RESET_BIT (U(1) << 28) 151 #define TEGRA_RST_DEV_CLR_V U(0x434) 152 #define TEGRA_CLK_ENB_V U(0x440) 153 154 /******************************************************************************* 155 * Tegra Flow Controller constants 156 ******************************************************************************/ 157 #define TEGRA_FLOWCTRL_BASE U(0x60007000) 158 159 /******************************************************************************* 160 * Tegra AHB arbitration controller 161 ******************************************************************************/ 162 #define TEGRA_AHB_ARB_BASE 0x6000C000UL 163 164 /******************************************************************************* 165 * Tegra Secure Boot Controller constants 166 ******************************************************************************/ 167 #define TEGRA_SB_BASE U(0x6000C200) 168 169 /******************************************************************************* 170 * Tegra Exception Vectors constants 171 ******************************************************************************/ 172 #define TEGRA_EVP_BASE U(0x6000F000) 173 174 /******************************************************************************* 175 * Tegra Miscellaneous register constants 176 ******************************************************************************/ 177 #define TEGRA_MISC_BASE U(0x70000000) 178 #define HARDWARE_REVISION_OFFSET U(0x804) 179 #define APB_SLAVE_SECURITY_ENABLE U(0xC00) 180 #define PMC_SECURITY_EN_BIT (U(1) << 13) 181 #define PINMUX_AUX_DVFS_PWM U(0x3184) 182 #define PINMUX_PWM_TRISTATE (U(1) << 4) 183 184 /******************************************************************************* 185 * Tegra UART controller base addresses 186 ******************************************************************************/ 187 #define TEGRA_UARTA_BASE U(0x70006000) 188 #define TEGRA_UARTB_BASE U(0x70006040) 189 #define TEGRA_UARTC_BASE U(0x70006200) 190 #define TEGRA_UARTD_BASE U(0x70006300) 191 #define TEGRA_UARTE_BASE U(0x70006400) 192 193 /******************************************************************************* 194 * Tegra Fuse Controller related constants 195 ******************************************************************************/ 196 #define TEGRA_FUSE_BASE 0x7000F800UL 197 #define FUSE_BOOT_SECURITY_INFO 0x268UL 198 #define FUSE_ATOMIC_SAVE_CARVEOUT_EN (0x1U << 7) 199 #define FUSE_JTAG_SECUREID_VALID (0x104UL) 200 #define ECID_VALID (0x1UL) 201 202 203 /******************************************************************************* 204 * Tegra Power Mgmt Controller constants 205 ******************************************************************************/ 206 #define TEGRA_PMC_BASE U(0x7000E400) 207 #define TEGRA_PMC_SIZE U(0xC00) /* 3k */ 208 209 /******************************************************************************* 210 * Tegra Atomics constants 211 ******************************************************************************/ 212 #define TEGRA_ATOMICS_BASE 0x70016000UL 213 #define TRIGGER0_REG_OFFSET 0UL 214 #define TRIGGER_WIDTH_SHIFT 4UL 215 #define TRIGGER_ID_SHIFT 16UL 216 #define RESULT0_REG_OFFSET 0xC00UL 217 218 /******************************************************************************* 219 * Tegra Memory Controller constants 220 ******************************************************************************/ 221 #define TEGRA_MC_BASE U(0x70019000) 222 223 /* Memory Controller Interrupt Status */ 224 #define MC_INTSTATUS 0x00U 225 226 /* TZDRAM carveout configuration registers */ 227 #define MC_SECURITY_CFG0_0 U(0x70) 228 #define MC_SECURITY_CFG1_0 U(0x74) 229 #define MC_SECURITY_CFG3_0 U(0x9BC) 230 231 /* Video Memory carveout configuration registers */ 232 #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 233 #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 234 #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) 235 236 /* SMMU configuration registers*/ 237 #define MC_SMMU_PPCS_ASID_0 0x270U 238 #define PPCS_SMMU_ENABLE (0x1U << 31) 239 240 /******************************************************************************* 241 * Tegra CLDVFS constants 242 ******************************************************************************/ 243 #define TEGRA_CL_DVFS_BASE U(0x70110000) 244 #define DVFS_DFLL_CTRL U(0x00) 245 #define ENABLE_OPEN_LOOP U(1) 246 #define ENABLE_CLOSED_LOOP U(2) 247 #define DVFS_DFLL_OUTPUT_CFG U(0x20) 248 #define DFLL_OUTPUT_CFG_I2C_EN_BIT (U(1) << 30) 249 #define DFLL_OUTPUT_CFG_CLK_EN_BIT (U(1) << 6) 250 251 /******************************************************************************* 252 * Tegra SE constants 253 ******************************************************************************/ 254 #define TEGRA_SE1_BASE U(0x70012000) 255 #define TEGRA_SE2_BASE U(0x70412000) 256 #define TEGRA_PKA1_BASE U(0x70420000) 257 #define TEGRA_SE2_RANGE_SIZE U(0x2000) 258 #define SE_TZRAM_SECURITY U(0x4) 259 260 /******************************************************************************* 261 * Tegra TZRAM constants 262 ******************************************************************************/ 263 #define TEGRA_TZRAM_BASE U(0x7C010000) 264 #define TEGRA_TZRAM_SIZE U(0x10000) 265 266 /******************************************************************************* 267 * Tegra TZRAM carveout constants 268 ******************************************************************************/ 269 #define TEGRA_TZRAM_CARVEOUT_BASE U(0x7C04C000) 270 #define TEGRA_TZRAM_CARVEOUT_SIZE U(0x4000) 271 272 /******************************************************************************* 273 * Tegra DRAM memory base address 274 ******************************************************************************/ 275 #define TEGRA_DRAM_BASE ULL(0x80000000) 276 #define TEGRA_DRAM_END ULL(0x27FFFFFFF) 277 278 #endif /* TEGRA_DEF_H */ 279