1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __TEGRA_DEF_H__ 8 #define __TEGRA_DEF_H__ 9 10 /******************************************************************************* 11 * Power down state IDs 12 ******************************************************************************/ 13 #define PSTATE_ID_CORE_POWERDN 7 14 #define PSTATE_ID_CLUSTER_IDLE 16 15 #define PSTATE_ID_CLUSTER_POWERDN 17 16 #define PSTATE_ID_SOC_POWERDN 27 17 18 /******************************************************************************* 19 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 20 * call as the `state-id` field in the 'power state' parameter. 21 ******************************************************************************/ 22 #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN 23 24 /******************************************************************************* 25 * Platform power states (used by PSCI framework) 26 * 27 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 28 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 29 ******************************************************************************/ 30 #define PLAT_MAX_RET_STATE 1 31 #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1) 32 33 /******************************************************************************* 34 * GIC memory map 35 ******************************************************************************/ 36 #define TEGRA_GICD_BASE 0x50041000 37 #define TEGRA_GICC_BASE 0x50042000 38 39 /******************************************************************************* 40 * Tegra Memory Select Switch Controller constants 41 ******************************************************************************/ 42 #define TEGRA_MSELECT_BASE 0x50060000 43 44 #define MSELECT_CONFIG 0x0 45 #define ENABLE_WRAP_INCR_MASTER2_BIT (1 << 29) 46 #define ENABLE_WRAP_INCR_MASTER1_BIT (1 << 28) 47 #define ENABLE_WRAP_INCR_MASTER0_BIT (1 << 27) 48 #define UNSUPPORTED_TX_ERR_MASTER2_BIT (1 << 25) 49 #define UNSUPPORTED_TX_ERR_MASTER1_BIT (1 << 24) 50 #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ 51 UNSUPPORTED_TX_ERR_MASTER1_BIT) 52 #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ 53 ENABLE_WRAP_INCR_MASTER1_BIT | \ 54 ENABLE_WRAP_INCR_MASTER0_BIT) 55 56 /******************************************************************************* 57 * Tegra micro-seconds timer constants 58 ******************************************************************************/ 59 #define TEGRA_TMRUS_BASE 0x60005010 60 #define TEGRA_TMRUS_SIZE 0x1000 61 62 /******************************************************************************* 63 * Tegra Clock and Reset Controller constants 64 ******************************************************************************/ 65 #define TEGRA_CAR_RESET_BASE 0x60006000 66 67 /******************************************************************************* 68 * Tegra Flow Controller constants 69 ******************************************************************************/ 70 #define TEGRA_FLOWCTRL_BASE 0x60007000 71 72 /******************************************************************************* 73 * Tegra Secure Boot Controller constants 74 ******************************************************************************/ 75 #define TEGRA_SB_BASE 0x6000C200 76 77 /******************************************************************************* 78 * Tegra Exception Vectors constants 79 ******************************************************************************/ 80 #define TEGRA_EVP_BASE 0x6000F000 81 82 /******************************************************************************* 83 * Tegra Miscellaneous register constants 84 ******************************************************************************/ 85 #define TEGRA_MISC_BASE 0x70000000 86 #define HARDWARE_REVISION_OFFSET 0x804 87 88 /******************************************************************************* 89 * Tegra UART controller base addresses 90 ******************************************************************************/ 91 #define TEGRA_UARTA_BASE 0x70006000 92 #define TEGRA_UARTB_BASE 0x70006040 93 #define TEGRA_UARTC_BASE 0x70006200 94 #define TEGRA_UARTD_BASE 0x70006300 95 #define TEGRA_UARTE_BASE 0x70006400 96 97 /******************************************************************************* 98 * Tegra Power Mgmt Controller constants 99 ******************************************************************************/ 100 #define TEGRA_PMC_BASE 0x7000E400 101 102 /******************************************************************************* 103 * Tegra Memory Controller constants 104 ******************************************************************************/ 105 #define TEGRA_MC_BASE 0x70019000 106 107 /* TZDRAM carveout configuration registers */ 108 #define MC_SECURITY_CFG0_0 0x70 109 #define MC_SECURITY_CFG1_0 0x74 110 #define MC_SECURITY_CFG3_0 0x9BC 111 112 /* Video Memory carveout configuration registers */ 113 #define MC_VIDEO_PROTECT_BASE_HI 0x978 114 #define MC_VIDEO_PROTECT_BASE_LO 0x648 115 #define MC_VIDEO_PROTECT_SIZE_MB 0x64c 116 117 /******************************************************************************* 118 * Tegra TZRAM constants 119 ******************************************************************************/ 120 #define TEGRA_TZRAM_BASE 0x7C010000 121 #define TEGRA_TZRAM_SIZE 0x10000 122 123 #endif /* __TEGRA_DEF_H__ */ 124