1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef TEGRA_DEF_H 9 #define TEGRA_DEF_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * Power down state IDs 15 ******************************************************************************/ 16 #define PSTATE_ID_CORE_POWERDN U(7) 17 #define PSTATE_ID_CLUSTER_IDLE U(16) 18 #define PSTATE_ID_SOC_POWERDN U(27) 19 20 /******************************************************************************* 21 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 22 * call as the `state-id` field in the 'power state' parameter. 23 ******************************************************************************/ 24 #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN 25 26 /******************************************************************************* 27 * Platform power states (used by PSCI framework) 28 * 29 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 30 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 31 ******************************************************************************/ 32 #define PLAT_MAX_RET_STATE U(1) 33 #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) 34 35 /******************************************************************************* 36 * Chip specific page table and MMU setup constants 37 ******************************************************************************/ 38 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) 39 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) 40 41 /******************************************************************************* 42 * SC7 entry firmware's header size 43 ******************************************************************************/ 44 #define SC7ENTRY_FW_HEADER_SIZE_BYTES U(0x400) 45 46 /******************************************************************************* 47 * Counter-timer physical secure timer PPI 48 ******************************************************************************/ 49 #define TEGRA210_TIMER1_IRQ 32 50 51 /******************************************************************************* 52 * iRAM memory constants 53 ******************************************************************************/ 54 #define TEGRA_IRAM_BASE U(0x40000000) 55 #define TEGRA_IRAM_A_SIZE U(0x10000) /* 64KB */ 56 #define TEGRA_IRAM_SIZE U(40000) /* 256KB */ 57 58 /******************************************************************************* 59 * GIC memory map 60 ******************************************************************************/ 61 #define TEGRA_GICD_BASE U(0x50041000) 62 #define TEGRA_GICC_BASE U(0x50042000) 63 64 /******************************************************************************* 65 * Secure IRQ definitions 66 ******************************************************************************/ 67 #define TEGRA210_WDT_CPU_LEGACY_FIQ U(28) 68 69 /******************************************************************************* 70 * Tegra Memory Select Switch Controller constants 71 ******************************************************************************/ 72 #define TEGRA_MSELECT_BASE U(0x50060000) 73 74 #define MSELECT_CONFIG U(0x0) 75 #define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29)) 76 #define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28)) 77 #define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27)) 78 #define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25)) 79 #define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24)) 80 #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ 81 UNSUPPORTED_TX_ERR_MASTER1_BIT) 82 #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ 83 ENABLE_WRAP_INCR_MASTER1_BIT | \ 84 ENABLE_WRAP_INCR_MASTER0_BIT) 85 86 /******************************************************************************* 87 * Tegra Resource Semaphore constants 88 ******************************************************************************/ 89 #define TEGRA_RES_SEMA_BASE 0x60001000UL 90 #define STA_OFFSET 0UL 91 #define SET_OFFSET 4UL 92 #define CLR_OFFSET 8UL 93 94 /******************************************************************************* 95 * Tegra Primary Interrupt Controller constants 96 ******************************************************************************/ 97 #define TEGRA_PRI_ICTLR_BASE 0x60004000UL 98 #define CPU_IEP_FIR_SET 0x18UL 99 100 /******************************************************************************* 101 * Tegra micro-seconds timer constants 102 ******************************************************************************/ 103 #define TEGRA_TMRUS_BASE U(0x60005010) 104 #define TEGRA_TMRUS_SIZE U(0x1000) 105 106 /******************************************************************************* 107 * Tegra Clock and Reset Controller constants 108 ******************************************************************************/ 109 #define TEGRA_CAR_RESET_BASE U(0x60006000) 110 #define TEGRA_BOND_OUT_H U(0x74) 111 #define APB_DMA_LOCK_BIT (U(1) << 2) 112 #define AHB_DMA_LOCK_BIT (U(1) << 1) 113 #define TEGRA_BOND_OUT_U U(0x78) 114 #define IRAM_D_LOCK_BIT (U(1) << 23) 115 #define IRAM_C_LOCK_BIT (U(1) << 22) 116 #define IRAM_B_LOCK_BIT (U(1) << 21) 117 #define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) 118 #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290) 119 #define GPU_RESET_BIT (U(1) << 24) 120 #define GPU_SET_BIT (U(1) << 24) 121 #define TEGRA_RST_DEV_SET_Y U(0x2a8) 122 #define NVENC_RESET_BIT (U(1) << 27) 123 #define TSECB_RESET_BIT (U(1) << 14) 124 #define APE_RESET_BIT (U(1) << 6) 125 #define NVJPG_RESET_BIT (U(1) << 3) 126 #define NVDEC_RESET_BIT (U(1) << 2) 127 #define TEGRA_RST_DEV_SET_L U(0x300) 128 #define HOST1X_RESET_BIT (U(1) << 28) 129 #define ISP_RESET_BIT (U(1) << 23) 130 #define USBD_RESET_BIT (U(1) << 22) 131 #define VI_RESET_BIT (U(1) << 20) 132 #define SDMMC4_RESET_BIT (U(1) << 15) 133 #define SDMMC1_RESET_BIT (U(1) << 14) 134 #define SDMMC2_RESET_BIT (U(1) << 9) 135 #define TEGRA_RST_DEV_SET_H U(0x308) 136 #define USB2_RESET_BIT (U(1) << 26) 137 #define APBDMA_RESET_BIT (U(1) << 2) 138 #define AHBDMA_RESET_BIT (U(1) << 1) 139 #define TEGRA_RST_DEV_SET_U U(0x310) 140 #define XUSB_DEV_RESET_BIT (U(1) << 31) 141 #define XUSB_HOST_RESET_BIT (U(1) << 25) 142 #define TSEC_RESET_BIT (U(1) << 19) 143 #define PCIE_RESET_BIT (U(1) << 6) 144 #define SDMMC3_RESET_BIT (U(1) << 5) 145 #define TEGRA_RST_DEVICES_V U(0x358) 146 #define TEGRA_RST_DEVICES_W U(0x35C) 147 #define ENTROPY_CLK_ENB_BIT (U(1) << 21) 148 #define TEGRA_CLK_OUT_ENB_V U(0x360) 149 #define SE_CLK_ENB_BIT (U(1) << 31) 150 #define TEGRA_CLK_OUT_ENB_W U(0x364) 151 #define ENTROPY_RESET_BIT (U(1) << 21) 152 #define TEGRA_CLK_RST_CTL_CLK_SRC_SE U(0x42C) 153 #define SE_CLK_SRC_MASK (U(7) << 29) 154 #define SE_CLK_SRC_CLK_M (U(6) << 29) 155 #define TEGRA_RST_DEV_SET_V U(0x430) 156 #define SE_RESET_BIT (U(1) << 31) 157 #define HDA_RESET_BIT (U(1) << 29) 158 #define SATA_RESET_BIT (U(1) << 28) 159 #define TEGRA_RST_DEV_CLR_V U(0x434) 160 #define TEGRA_CLK_ENB_V U(0x440) 161 162 /******************************************************************************* 163 * Tegra Flow Controller constants 164 ******************************************************************************/ 165 #define TEGRA_FLOWCTRL_BASE U(0x60007000) 166 167 /******************************************************************************* 168 * Tegra AHB arbitration controller 169 ******************************************************************************/ 170 #define TEGRA_AHB_ARB_BASE 0x6000C000UL 171 172 /******************************************************************************* 173 * Tegra Secure Boot Controller constants 174 ******************************************************************************/ 175 #define TEGRA_SB_BASE U(0x6000C200) 176 177 /******************************************************************************* 178 * Tegra Exception Vectors constants 179 ******************************************************************************/ 180 #define TEGRA_EVP_BASE U(0x6000F000) 181 182 /******************************************************************************* 183 * Tegra Miscellaneous register constants 184 ******************************************************************************/ 185 #define TEGRA_MISC_BASE U(0x70000000) 186 #define HARDWARE_REVISION_OFFSET U(0x804) 187 #define APB_SLAVE_SECURITY_ENABLE U(0xC00) 188 #define PMC_SECURITY_EN_BIT (U(1) << 13) 189 #define PINMUX_AUX_DVFS_PWM U(0x3184) 190 #define PINMUX_PWM_TRISTATE (U(1) << 4) 191 192 /******************************************************************************* 193 * Tegra UART controller base addresses 194 ******************************************************************************/ 195 #define TEGRA_UARTA_BASE U(0x70006000) 196 #define TEGRA_UARTB_BASE U(0x70006040) 197 #define TEGRA_UARTC_BASE U(0x70006200) 198 #define TEGRA_UARTD_BASE U(0x70006300) 199 #define TEGRA_UARTE_BASE U(0x70006400) 200 201 /******************************************************************************* 202 * Tegra Fuse Controller related constants 203 ******************************************************************************/ 204 #define TEGRA_FUSE_BASE 0x7000F800UL 205 #define FUSE_BOOT_SECURITY_INFO 0x268UL 206 #define FUSE_ATOMIC_SAVE_CARVEOUT_EN (0x1U << 7) 207 #define FUSE_JTAG_SECUREID_VALID (0x104UL) 208 #define ECID_VALID (0x1UL) 209 210 211 /******************************************************************************* 212 * Tegra Power Mgmt Controller constants 213 ******************************************************************************/ 214 #define TEGRA_PMC_BASE U(0x7000E400) 215 #define TEGRA_PMC_SIZE U(0xC00) /* 3k */ 216 217 /******************************************************************************* 218 * Tegra Atomics constants 219 ******************************************************************************/ 220 #define TEGRA_ATOMICS_BASE 0x70016000UL 221 #define TRIGGER0_REG_OFFSET 0UL 222 #define TRIGGER_WIDTH_SHIFT 4UL 223 #define TRIGGER_ID_SHIFT 16UL 224 #define RESULT0_REG_OFFSET 0xC00UL 225 226 /******************************************************************************* 227 * Tegra Memory Controller constants 228 ******************************************************************************/ 229 #define TEGRA_MC_BASE U(0x70019000) 230 231 /* Memory Controller Interrupt Status */ 232 #define MC_INTSTATUS 0x00U 233 234 /* TZDRAM carveout configuration registers */ 235 #define MC_SECURITY_CFG0_0 U(0x70) 236 #define MC_SECURITY_CFG1_0 U(0x74) 237 #define MC_SECURITY_CFG3_0 U(0x9BC) 238 239 /* Video Memory carveout configuration registers */ 240 #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 241 #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 242 #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) 243 244 /* SMMU configuration registers*/ 245 #define MC_SMMU_PPCS_ASID_0 0x270U 246 #define PPCS_SMMU_ENABLE (0x1U << 31) 247 248 /******************************************************************************* 249 * Tegra CLDVFS constants 250 ******************************************************************************/ 251 #define TEGRA_CL_DVFS_BASE U(0x70110000) 252 #define DVFS_DFLL_CTRL U(0x00) 253 #define ENABLE_OPEN_LOOP U(1) 254 #define ENABLE_CLOSED_LOOP U(2) 255 #define DVFS_DFLL_OUTPUT_CFG U(0x20) 256 #define DFLL_OUTPUT_CFG_I2C_EN_BIT (U(1) << 30) 257 #define DFLL_OUTPUT_CFG_CLK_EN_BIT (U(1) << 6) 258 259 /******************************************************************************* 260 * Tegra SE constants 261 ******************************************************************************/ 262 #define TEGRA_SE1_BASE U(0x70012000) 263 #define TEGRA_SE2_BASE U(0x70412000) 264 #define TEGRA_PKA1_BASE U(0x70420000) 265 #define TEGRA_SE2_RANGE_SIZE U(0x2000) 266 #define SE_TZRAM_SECURITY U(0x4) 267 268 /******************************************************************************* 269 * Tegra TZRAM constants 270 ******************************************************************************/ 271 #define TEGRA_TZRAM_BASE U(0x7C010000) 272 #define TEGRA_TZRAM_SIZE U(0x10000) 273 274 /******************************************************************************* 275 * Tegra TZRAM carveout constants 276 ******************************************************************************/ 277 #define TEGRA_TZRAM_CARVEOUT_BASE U(0x7C04C000) 278 #define TEGRA_TZRAM_CARVEOUT_SIZE U(0x4000) 279 280 /******************************************************************************* 281 * Tegra DRAM memory base address 282 ******************************************************************************/ 283 #define TEGRA_DRAM_BASE ULL(0x80000000) 284 #define TEGRA_DRAM_END ULL(0x27FFFFFFF) 285 286 #endif /* TEGRA_DEF_H */ 287