108438e24SVarun Wadekar /* 206b19d58SVarun Wadekar * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 408438e24SVarun Wadekar * Redistribution and use in source and binary forms, with or without 508438e24SVarun Wadekar * modification, are permitted provided that the following conditions are met: 608438e24SVarun Wadekar * 708438e24SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 808438e24SVarun Wadekar * list of conditions and the following disclaimer. 908438e24SVarun Wadekar * 1008438e24SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 1108438e24SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 1208438e24SVarun Wadekar * and/or other materials provided with the distribution. 1308438e24SVarun Wadekar * 1408438e24SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 1508438e24SVarun Wadekar * to endorse or promote products derived from this software without specific 1608438e24SVarun Wadekar * prior written permission. 1708438e24SVarun Wadekar * 1808438e24SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1908438e24SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2008438e24SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2108438e24SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2208438e24SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2308438e24SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2408438e24SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2508438e24SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2608438e24SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2708438e24SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2808438e24SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 2908438e24SVarun Wadekar */ 3008438e24SVarun Wadekar 3108438e24SVarun Wadekar #ifndef __TEGRA_DEF_H__ 3208438e24SVarun Wadekar #define __TEGRA_DEF_H__ 3308438e24SVarun Wadekar 3408438e24SVarun Wadekar #include <platform_def.h> 3508438e24SVarun Wadekar 3608438e24SVarun Wadekar /******************************************************************************* 3794c672e7SVarun Wadekar * Power down state IDs 3894c672e7SVarun Wadekar ******************************************************************************/ 3994c672e7SVarun Wadekar #define PSTATE_ID_CORE_POWERDN 7 4094c672e7SVarun Wadekar #define PSTATE_ID_CLUSTER_IDLE 16 4194c672e7SVarun Wadekar #define PSTATE_ID_CLUSTER_POWERDN 17 4294c672e7SVarun Wadekar #define PSTATE_ID_SOC_POWERDN 27 4394c672e7SVarun Wadekar 4494c672e7SVarun Wadekar /******************************************************************************* 4594c672e7SVarun Wadekar * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 4694c672e7SVarun Wadekar * call as the `state-id` field in the 'power state' parameter. 4794c672e7SVarun Wadekar ******************************************************************************/ 4894c672e7SVarun Wadekar #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN 4994c672e7SVarun Wadekar 5094c672e7SVarun Wadekar /******************************************************************************* 519f9bafa3SVarun Wadekar * Platform power states (used by PSCI framework) 529f9bafa3SVarun Wadekar * 539f9bafa3SVarun Wadekar * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 549f9bafa3SVarun Wadekar * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 559f9bafa3SVarun Wadekar ******************************************************************************/ 569f9bafa3SVarun Wadekar #define PLAT_MAX_RET_STATE 1 579f9bafa3SVarun Wadekar #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1) 589f9bafa3SVarun Wadekar 599f9bafa3SVarun Wadekar /******************************************************************************* 6008438e24SVarun Wadekar * GIC memory map 6108438e24SVarun Wadekar ******************************************************************************/ 6208438e24SVarun Wadekar #define TEGRA_GICD_BASE 0x50041000 6308438e24SVarun Wadekar #define TEGRA_GICC_BASE 0x50042000 6408438e24SVarun Wadekar 6508438e24SVarun Wadekar /******************************************************************************* 6642ca2d86SVarun Wadekar * Tegra Memory Select Switch Controller constants 6742ca2d86SVarun Wadekar ******************************************************************************/ 6842ca2d86SVarun Wadekar #define TEGRA_MSELECT_BASE 0x50060000 6942ca2d86SVarun Wadekar 7042ca2d86SVarun Wadekar #define MSELECT_CONFIG 0x0 7142ca2d86SVarun Wadekar #define ENABLE_WRAP_INCR_MASTER2_BIT (1 << 29) 7242ca2d86SVarun Wadekar #define ENABLE_WRAP_INCR_MASTER1_BIT (1 << 28) 7342ca2d86SVarun Wadekar #define ENABLE_WRAP_INCR_MASTER0_BIT (1 << 27) 7442ca2d86SVarun Wadekar #define UNSUPPORTED_TX_ERR_MASTER2_BIT (1 << 25) 7542ca2d86SVarun Wadekar #define UNSUPPORTED_TX_ERR_MASTER1_BIT (1 << 24) 7642ca2d86SVarun Wadekar #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ 7742ca2d86SVarun Wadekar UNSUPPORTED_TX_ERR_MASTER1_BIT) 7842ca2d86SVarun Wadekar #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ 7942ca2d86SVarun Wadekar ENABLE_WRAP_INCR_MASTER1_BIT | \ 8042ca2d86SVarun Wadekar ENABLE_WRAP_INCR_MASTER0_BIT) 8142ca2d86SVarun Wadekar 8242ca2d86SVarun Wadekar /******************************************************************************* 8308438e24SVarun Wadekar * Tegra micro-seconds timer constants 8408438e24SVarun Wadekar ******************************************************************************/ 8508438e24SVarun Wadekar #define TEGRA_TMRUS_BASE 0x60005010 8608438e24SVarun Wadekar 8708438e24SVarun Wadekar /******************************************************************************* 8808438e24SVarun Wadekar * Tegra Clock and Reset Controller constants 8908438e24SVarun Wadekar ******************************************************************************/ 9008438e24SVarun Wadekar #define TEGRA_CAR_RESET_BASE 0x60006000 9108438e24SVarun Wadekar 9208438e24SVarun Wadekar /******************************************************************************* 9308438e24SVarun Wadekar * Tegra Flow Controller constants 9408438e24SVarun Wadekar ******************************************************************************/ 9508438e24SVarun Wadekar #define TEGRA_FLOWCTRL_BASE 0x60007000 9608438e24SVarun Wadekar 9708438e24SVarun Wadekar /******************************************************************************* 9808438e24SVarun Wadekar * Tegra Secure Boot Controller constants 9908438e24SVarun Wadekar ******************************************************************************/ 10008438e24SVarun Wadekar #define TEGRA_SB_BASE 0x6000C200 10108438e24SVarun Wadekar 10208438e24SVarun Wadekar /******************************************************************************* 10308438e24SVarun Wadekar * Tegra Exception Vectors constants 10408438e24SVarun Wadekar ******************************************************************************/ 10508438e24SVarun Wadekar #define TEGRA_EVP_BASE 0x6000F000 10608438e24SVarun Wadekar 10708438e24SVarun Wadekar /******************************************************************************* 108*e954ab8fSVarun Wadekar * Tegra Miscellaneous register constants 109*e954ab8fSVarun Wadekar ******************************************************************************/ 110*e954ab8fSVarun Wadekar #define TEGRA_MISC_BASE 0x70000000 111*e954ab8fSVarun Wadekar #define HARDWARE_REVISION_OFFSET 0x804 112*e954ab8fSVarun Wadekar 113*e954ab8fSVarun Wadekar /******************************************************************************* 114e1084216SVarun Wadekar * Tegra UART controller base addresses 115e1084216SVarun Wadekar ******************************************************************************/ 116e1084216SVarun Wadekar #define TEGRA_UARTA_BASE 0x70006000 117e1084216SVarun Wadekar #define TEGRA_UARTB_BASE 0x70006040 118e1084216SVarun Wadekar #define TEGRA_UARTC_BASE 0x70006200 119e1084216SVarun Wadekar #define TEGRA_UARTD_BASE 0x70006300 120e1084216SVarun Wadekar #define TEGRA_UARTE_BASE 0x70006400 121e1084216SVarun Wadekar 122e1084216SVarun Wadekar /******************************************************************************* 12308438e24SVarun Wadekar * Tegra Power Mgmt Controller constants 12408438e24SVarun Wadekar ******************************************************************************/ 12508438e24SVarun Wadekar #define TEGRA_PMC_BASE 0x7000E400 12608438e24SVarun Wadekar 12708438e24SVarun Wadekar /******************************************************************************* 12808438e24SVarun Wadekar * Tegra Memory Controller constants 12908438e24SVarun Wadekar ******************************************************************************/ 13008438e24SVarun Wadekar #define TEGRA_MC_BASE 0x70019000 13108438e24SVarun Wadekar 13206b19d58SVarun Wadekar /******************************************************************************* 13306b19d58SVarun Wadekar * Tegra TZRAM constants 13406b19d58SVarun Wadekar ******************************************************************************/ 13506b19d58SVarun Wadekar #define TEGRA_TZRAM_BASE 0x7C010000 13606b19d58SVarun Wadekar #define TEGRA_TZRAM_SIZE 0x10000 13706b19d58SVarun Wadekar 13808438e24SVarun Wadekar #endif /* __TEGRA_DEF_H__ */ 139