108438e24SVarun Wadekar /* 2e99eeec6SSteven Kao * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 7c3cf06f1SAntonio Nino Diaz #ifndef TEGRA_DEF_H 8c3cf06f1SAntonio Nino Diaz #define TEGRA_DEF_H 908438e24SVarun Wadekar 1009d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 1170cb692eSVarun Wadekar 1208438e24SVarun Wadekar /******************************************************************************* 1394c672e7SVarun Wadekar * Power down state IDs 1494c672e7SVarun Wadekar ******************************************************************************/ 1570cb692eSVarun Wadekar #define PSTATE_ID_CORE_POWERDN U(7) 1670cb692eSVarun Wadekar #define PSTATE_ID_CLUSTER_IDLE U(16) 1770cb692eSVarun Wadekar #define PSTATE_ID_CLUSTER_POWERDN U(17) 1870cb692eSVarun Wadekar #define PSTATE_ID_SOC_POWERDN U(27) 1994c672e7SVarun Wadekar 2094c672e7SVarun Wadekar /******************************************************************************* 2194c672e7SVarun Wadekar * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 2294c672e7SVarun Wadekar * call as the `state-id` field in the 'power state' parameter. 2394c672e7SVarun Wadekar ******************************************************************************/ 2494c672e7SVarun Wadekar #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN 2594c672e7SVarun Wadekar 2694c672e7SVarun Wadekar /******************************************************************************* 279f9bafa3SVarun Wadekar * Platform power states (used by PSCI framework) 289f9bafa3SVarun Wadekar * 299f9bafa3SVarun Wadekar * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 309f9bafa3SVarun Wadekar * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 319f9bafa3SVarun Wadekar ******************************************************************************/ 3270cb692eSVarun Wadekar #define PLAT_MAX_RET_STATE U(1) 3370cb692eSVarun Wadekar #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) 349f9bafa3SVarun Wadekar 359f9bafa3SVarun Wadekar /******************************************************************************* 36*dd1a71f1SVarun Wadekar * iRAM memory constants 37*dd1a71f1SVarun Wadekar ******************************************************************************/ 38*dd1a71f1SVarun Wadekar #define TEGRA_IRAMA_BASE 0x40000000 39*dd1a71f1SVarun Wadekar #define TEGRA_IRAMB_BASE 0x40010000 40*dd1a71f1SVarun Wadekar 41*dd1a71f1SVarun Wadekar /******************************************************************************* 4208438e24SVarun Wadekar * GIC memory map 4308438e24SVarun Wadekar ******************************************************************************/ 4470cb692eSVarun Wadekar #define TEGRA_GICD_BASE U(0x50041000) 4570cb692eSVarun Wadekar #define TEGRA_GICC_BASE U(0x50042000) 4608438e24SVarun Wadekar 4708438e24SVarun Wadekar /******************************************************************************* 4842ca2d86SVarun Wadekar * Tegra Memory Select Switch Controller constants 4942ca2d86SVarun Wadekar ******************************************************************************/ 5070cb692eSVarun Wadekar #define TEGRA_MSELECT_BASE U(0x50060000) 5142ca2d86SVarun Wadekar 5270cb692eSVarun Wadekar #define MSELECT_CONFIG U(0x0) 5370cb692eSVarun Wadekar #define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29)) 5470cb692eSVarun Wadekar #define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28)) 5570cb692eSVarun Wadekar #define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27)) 5670cb692eSVarun Wadekar #define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25)) 5770cb692eSVarun Wadekar #define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24)) 5842ca2d86SVarun Wadekar #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ 5942ca2d86SVarun Wadekar UNSUPPORTED_TX_ERR_MASTER1_BIT) 6042ca2d86SVarun Wadekar #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ 6142ca2d86SVarun Wadekar ENABLE_WRAP_INCR_MASTER1_BIT | \ 6242ca2d86SVarun Wadekar ENABLE_WRAP_INCR_MASTER0_BIT) 6342ca2d86SVarun Wadekar 6442ca2d86SVarun Wadekar /******************************************************************************* 65*dd1a71f1SVarun Wadekar * Tegra Resource Semaphore constants 66*dd1a71f1SVarun Wadekar ******************************************************************************/ 67*dd1a71f1SVarun Wadekar #define TEGRA_RES_SEMA_BASE 0x60001000UL 68*dd1a71f1SVarun Wadekar #define STA_OFFSET 0UL 69*dd1a71f1SVarun Wadekar #define SET_OFFSET 4UL 70*dd1a71f1SVarun Wadekar #define CLR_OFFSET 8UL 71*dd1a71f1SVarun Wadekar 72*dd1a71f1SVarun Wadekar /******************************************************************************* 73*dd1a71f1SVarun Wadekar * Tegra Primary Interrupt Controller constants 74*dd1a71f1SVarun Wadekar ******************************************************************************/ 75*dd1a71f1SVarun Wadekar #define TEGRA_PRI_ICTLR_BASE 0x60004000UL 76*dd1a71f1SVarun Wadekar #define CPU_IEP_FIR_SET 0x18UL 77*dd1a71f1SVarun Wadekar 78*dd1a71f1SVarun Wadekar /******************************************************************************* 7908438e24SVarun Wadekar * Tegra micro-seconds timer constants 8008438e24SVarun Wadekar ******************************************************************************/ 8170cb692eSVarun Wadekar #define TEGRA_TMRUS_BASE U(0x60005010) 8270cb692eSVarun Wadekar #define TEGRA_TMRUS_SIZE U(0x1000) 8308438e24SVarun Wadekar 8408438e24SVarun Wadekar /******************************************************************************* 8508438e24SVarun Wadekar * Tegra Clock and Reset Controller constants 8608438e24SVarun Wadekar ******************************************************************************/ 8770cb692eSVarun Wadekar #define TEGRA_CAR_RESET_BASE U(0x60006000) 88f5f64e4dSVarun Wadekar #define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) 89f5f64e4dSVarun Wadekar #define GPU_RESET_BIT (U(1) << 24) 90*dd1a71f1SVarun Wadekar #define TEGRA_RST_DEV_CLR_V U(0x434) 91*dd1a71f1SVarun Wadekar #define TEGRA_CLK_ENB_V U(0x440) 9208438e24SVarun Wadekar 9308438e24SVarun Wadekar /******************************************************************************* 9408438e24SVarun Wadekar * Tegra Flow Controller constants 9508438e24SVarun Wadekar ******************************************************************************/ 9670cb692eSVarun Wadekar #define TEGRA_FLOWCTRL_BASE U(0x60007000) 9708438e24SVarun Wadekar 9808438e24SVarun Wadekar /******************************************************************************* 99ce3c97c9SMarvin Hsu * Tegra AHB arbitration controller 100ce3c97c9SMarvin Hsu ******************************************************************************/ 101ce3c97c9SMarvin Hsu #define TEGRA_AHB_ARB_BASE 0x6000C000UL 102ce3c97c9SMarvin Hsu 103ce3c97c9SMarvin Hsu /******************************************************************************* 10408438e24SVarun Wadekar * Tegra Secure Boot Controller constants 10508438e24SVarun Wadekar ******************************************************************************/ 10670cb692eSVarun Wadekar #define TEGRA_SB_BASE U(0x6000C200) 10708438e24SVarun Wadekar 10808438e24SVarun Wadekar /******************************************************************************* 10908438e24SVarun Wadekar * Tegra Exception Vectors constants 11008438e24SVarun Wadekar ******************************************************************************/ 11170cb692eSVarun Wadekar #define TEGRA_EVP_BASE U(0x6000F000) 11208438e24SVarun Wadekar 11308438e24SVarun Wadekar /******************************************************************************* 114e954ab8fSVarun Wadekar * Tegra Miscellaneous register constants 115e954ab8fSVarun Wadekar ******************************************************************************/ 11670cb692eSVarun Wadekar #define TEGRA_MISC_BASE U(0x70000000) 11770cb692eSVarun Wadekar #define HARDWARE_REVISION_OFFSET U(0x804) 118e954ab8fSVarun Wadekar 119e954ab8fSVarun Wadekar /******************************************************************************* 120e1084216SVarun Wadekar * Tegra UART controller base addresses 121e1084216SVarun Wadekar ******************************************************************************/ 12270cb692eSVarun Wadekar #define TEGRA_UARTA_BASE U(0x70006000) 12370cb692eSVarun Wadekar #define TEGRA_UARTB_BASE U(0x70006040) 12470cb692eSVarun Wadekar #define TEGRA_UARTC_BASE U(0x70006200) 12570cb692eSVarun Wadekar #define TEGRA_UARTD_BASE U(0x70006300) 12670cb692eSVarun Wadekar #define TEGRA_UARTE_BASE U(0x70006400) 127e1084216SVarun Wadekar 128e1084216SVarun Wadekar /******************************************************************************* 12908438e24SVarun Wadekar * Tegra Power Mgmt Controller constants 13008438e24SVarun Wadekar ******************************************************************************/ 13170cb692eSVarun Wadekar #define TEGRA_PMC_BASE U(0x7000E400) 13208438e24SVarun Wadekar 13308438e24SVarun Wadekar /******************************************************************************* 134*dd1a71f1SVarun Wadekar * Tegra Atomics constants 135*dd1a71f1SVarun Wadekar ******************************************************************************/ 136*dd1a71f1SVarun Wadekar #define TEGRA_ATOMICS_BASE 0x70016000UL 137*dd1a71f1SVarun Wadekar #define TRIGGER0_REG_OFFSET 0UL 138*dd1a71f1SVarun Wadekar #define TRIGGER_WIDTH_SHIFT 4UL 139*dd1a71f1SVarun Wadekar #define TRIGGER_ID_SHIFT 16UL 140*dd1a71f1SVarun Wadekar #define RESULT0_REG_OFFSET 0xC00UL 141*dd1a71f1SVarun Wadekar 142*dd1a71f1SVarun Wadekar /******************************************************************************* 14308438e24SVarun Wadekar * Tegra Memory Controller constants 14408438e24SVarun Wadekar ******************************************************************************/ 14570cb692eSVarun Wadekar #define TEGRA_MC_BASE U(0x70019000) 14608438e24SVarun Wadekar 1470258840eSVarun Wadekar /* TZDRAM carveout configuration registers */ 14870cb692eSVarun Wadekar #define MC_SECURITY_CFG0_0 U(0x70) 14970cb692eSVarun Wadekar #define MC_SECURITY_CFG1_0 U(0x74) 15070cb692eSVarun Wadekar #define MC_SECURITY_CFG3_0 U(0x9BC) 1510258840eSVarun Wadekar 1520258840eSVarun Wadekar /* Video Memory carveout configuration registers */ 15370cb692eSVarun Wadekar #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 15470cb692eSVarun Wadekar #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 15570cb692eSVarun Wadekar #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) 1560258840eSVarun Wadekar 15706b19d58SVarun Wadekar /******************************************************************************* 158ce3c97c9SMarvin Hsu * Tegra SE constants 159ce3c97c9SMarvin Hsu ******************************************************************************/ 160ce3c97c9SMarvin Hsu #define TEGRA_SE1_BASE U(0x70012000) 161ce3c97c9SMarvin Hsu #define TEGRA_SE2_BASE U(0x70412000) 162ce3c97c9SMarvin Hsu #define TEGRA_PKA1_BASE U(0x70420000) 163ce3c97c9SMarvin Hsu #define TEGRA_SE2_RANGE_SIZE U(0x2000) 164ce3c97c9SMarvin Hsu #define SE_TZRAM_SECURITY U(0x4) 165ce3c97c9SMarvin Hsu 166ce3c97c9SMarvin Hsu /******************************************************************************* 16706b19d58SVarun Wadekar * Tegra TZRAM constants 16806b19d58SVarun Wadekar ******************************************************************************/ 16970cb692eSVarun Wadekar #define TEGRA_TZRAM_BASE U(0x7C010000) 17070cb692eSVarun Wadekar #define TEGRA_TZRAM_SIZE U(0x10000) 17106b19d58SVarun Wadekar 172c3cf06f1SAntonio Nino Diaz #endif /* TEGRA_DEF_H */ 173