108438e24SVarun Wadekar /* 2e99eeec6SSteven Kao * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 708438e24SVarun Wadekar #ifndef __TEGRA_DEF_H__ 808438e24SVarun Wadekar #define __TEGRA_DEF_H__ 908438e24SVarun Wadekar 1008438e24SVarun Wadekar #include <platform_def.h> 1108438e24SVarun Wadekar 1208438e24SVarun Wadekar /******************************************************************************* 1394c672e7SVarun Wadekar * Power down state IDs 1494c672e7SVarun Wadekar ******************************************************************************/ 1594c672e7SVarun Wadekar #define PSTATE_ID_CORE_POWERDN 7 1694c672e7SVarun Wadekar #define PSTATE_ID_CLUSTER_IDLE 16 1794c672e7SVarun Wadekar #define PSTATE_ID_CLUSTER_POWERDN 17 1894c672e7SVarun Wadekar #define PSTATE_ID_SOC_POWERDN 27 1994c672e7SVarun Wadekar 2094c672e7SVarun Wadekar /******************************************************************************* 2194c672e7SVarun Wadekar * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 2294c672e7SVarun Wadekar * call as the `state-id` field in the 'power state' parameter. 2394c672e7SVarun Wadekar ******************************************************************************/ 2494c672e7SVarun Wadekar #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN 2594c672e7SVarun Wadekar 2694c672e7SVarun Wadekar /******************************************************************************* 279f9bafa3SVarun Wadekar * Platform power states (used by PSCI framework) 289f9bafa3SVarun Wadekar * 299f9bafa3SVarun Wadekar * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 309f9bafa3SVarun Wadekar * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 319f9bafa3SVarun Wadekar ******************************************************************************/ 329f9bafa3SVarun Wadekar #define PLAT_MAX_RET_STATE 1 339f9bafa3SVarun Wadekar #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1) 349f9bafa3SVarun Wadekar 359f9bafa3SVarun Wadekar /******************************************************************************* 3608438e24SVarun Wadekar * GIC memory map 3708438e24SVarun Wadekar ******************************************************************************/ 3808438e24SVarun Wadekar #define TEGRA_GICD_BASE 0x50041000 3908438e24SVarun Wadekar #define TEGRA_GICC_BASE 0x50042000 4008438e24SVarun Wadekar 4108438e24SVarun Wadekar /******************************************************************************* 4242ca2d86SVarun Wadekar * Tegra Memory Select Switch Controller constants 4342ca2d86SVarun Wadekar ******************************************************************************/ 4442ca2d86SVarun Wadekar #define TEGRA_MSELECT_BASE 0x50060000 4542ca2d86SVarun Wadekar 4642ca2d86SVarun Wadekar #define MSELECT_CONFIG 0x0 4742ca2d86SVarun Wadekar #define ENABLE_WRAP_INCR_MASTER2_BIT (1 << 29) 4842ca2d86SVarun Wadekar #define ENABLE_WRAP_INCR_MASTER1_BIT (1 << 28) 4942ca2d86SVarun Wadekar #define ENABLE_WRAP_INCR_MASTER0_BIT (1 << 27) 5042ca2d86SVarun Wadekar #define UNSUPPORTED_TX_ERR_MASTER2_BIT (1 << 25) 5142ca2d86SVarun Wadekar #define UNSUPPORTED_TX_ERR_MASTER1_BIT (1 << 24) 5242ca2d86SVarun Wadekar #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ 5342ca2d86SVarun Wadekar UNSUPPORTED_TX_ERR_MASTER1_BIT) 5442ca2d86SVarun Wadekar #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ 5542ca2d86SVarun Wadekar ENABLE_WRAP_INCR_MASTER1_BIT | \ 5642ca2d86SVarun Wadekar ENABLE_WRAP_INCR_MASTER0_BIT) 5742ca2d86SVarun Wadekar 5842ca2d86SVarun Wadekar /******************************************************************************* 5908438e24SVarun Wadekar * Tegra micro-seconds timer constants 6008438e24SVarun Wadekar ******************************************************************************/ 6108438e24SVarun Wadekar #define TEGRA_TMRUS_BASE 0x60005010 62e99eeec6SSteven Kao #define TEGRA_TMRUS_SIZE 0x1000 6308438e24SVarun Wadekar 6408438e24SVarun Wadekar /******************************************************************************* 6508438e24SVarun Wadekar * Tegra Clock and Reset Controller constants 6608438e24SVarun Wadekar ******************************************************************************/ 6708438e24SVarun Wadekar #define TEGRA_CAR_RESET_BASE 0x60006000 6808438e24SVarun Wadekar 6908438e24SVarun Wadekar /******************************************************************************* 7008438e24SVarun Wadekar * Tegra Flow Controller constants 7108438e24SVarun Wadekar ******************************************************************************/ 7208438e24SVarun Wadekar #define TEGRA_FLOWCTRL_BASE 0x60007000 7308438e24SVarun Wadekar 7408438e24SVarun Wadekar /******************************************************************************* 7508438e24SVarun Wadekar * Tegra Secure Boot Controller constants 7608438e24SVarun Wadekar ******************************************************************************/ 7708438e24SVarun Wadekar #define TEGRA_SB_BASE 0x6000C200 7808438e24SVarun Wadekar 7908438e24SVarun Wadekar /******************************************************************************* 8008438e24SVarun Wadekar * Tegra Exception Vectors constants 8108438e24SVarun Wadekar ******************************************************************************/ 8208438e24SVarun Wadekar #define TEGRA_EVP_BASE 0x6000F000 8308438e24SVarun Wadekar 8408438e24SVarun Wadekar /******************************************************************************* 85e954ab8fSVarun Wadekar * Tegra Miscellaneous register constants 86e954ab8fSVarun Wadekar ******************************************************************************/ 87e954ab8fSVarun Wadekar #define TEGRA_MISC_BASE 0x70000000 88e954ab8fSVarun Wadekar #define HARDWARE_REVISION_OFFSET 0x804 89e954ab8fSVarun Wadekar 90e954ab8fSVarun Wadekar /******************************************************************************* 91e1084216SVarun Wadekar * Tegra UART controller base addresses 92e1084216SVarun Wadekar ******************************************************************************/ 93e1084216SVarun Wadekar #define TEGRA_UARTA_BASE 0x70006000 94e1084216SVarun Wadekar #define TEGRA_UARTB_BASE 0x70006040 95e1084216SVarun Wadekar #define TEGRA_UARTC_BASE 0x70006200 96e1084216SVarun Wadekar #define TEGRA_UARTD_BASE 0x70006300 97e1084216SVarun Wadekar #define TEGRA_UARTE_BASE 0x70006400 98e1084216SVarun Wadekar 99e1084216SVarun Wadekar /******************************************************************************* 10008438e24SVarun Wadekar * Tegra Power Mgmt Controller constants 10108438e24SVarun Wadekar ******************************************************************************/ 10208438e24SVarun Wadekar #define TEGRA_PMC_BASE 0x7000E400 10308438e24SVarun Wadekar 10408438e24SVarun Wadekar /******************************************************************************* 10508438e24SVarun Wadekar * Tegra Memory Controller constants 10608438e24SVarun Wadekar ******************************************************************************/ 10708438e24SVarun Wadekar #define TEGRA_MC_BASE 0x70019000 10808438e24SVarun Wadekar 1090258840eSVarun Wadekar /* TZDRAM carveout configuration registers */ 1100258840eSVarun Wadekar #define MC_SECURITY_CFG0_0 0x70 1110258840eSVarun Wadekar #define MC_SECURITY_CFG1_0 0x74 1120258840eSVarun Wadekar #define MC_SECURITY_CFG3_0 0x9BC 1130258840eSVarun Wadekar 1140258840eSVarun Wadekar /* Video Memory carveout configuration registers */ 1150258840eSVarun Wadekar #define MC_VIDEO_PROTECT_BASE_HI 0x978 1160258840eSVarun Wadekar #define MC_VIDEO_PROTECT_BASE_LO 0x648 1170258840eSVarun Wadekar #define MC_VIDEO_PROTECT_SIZE_MB 0x64c 1180258840eSVarun Wadekar 11906b19d58SVarun Wadekar /******************************************************************************* 12006b19d58SVarun Wadekar * Tegra TZRAM constants 12106b19d58SVarun Wadekar ******************************************************************************/ 12206b19d58SVarun Wadekar #define TEGRA_TZRAM_BASE 0x7C010000 12306b19d58SVarun Wadekar #define TEGRA_TZRAM_SIZE 0x10000 12406b19d58SVarun Wadekar 12508438e24SVarun Wadekar #endif /* __TEGRA_DEF_H__ */ 126