108438e24SVarun Wadekar /* 2e99eeec6SSteven Kao * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 708438e24SVarun Wadekar #ifndef __TEGRA_DEF_H__ 808438e24SVarun Wadekar #define __TEGRA_DEF_H__ 908438e24SVarun Wadekar 10*70cb692eSVarun Wadekar #include <utils_def.h> 11*70cb692eSVarun Wadekar 1208438e24SVarun Wadekar /******************************************************************************* 1394c672e7SVarun Wadekar * Power down state IDs 1494c672e7SVarun Wadekar ******************************************************************************/ 15*70cb692eSVarun Wadekar #define PSTATE_ID_CORE_POWERDN U(7) 16*70cb692eSVarun Wadekar #define PSTATE_ID_CLUSTER_IDLE U(16) 17*70cb692eSVarun Wadekar #define PSTATE_ID_CLUSTER_POWERDN U(17) 18*70cb692eSVarun Wadekar #define PSTATE_ID_SOC_POWERDN U(27) 1994c672e7SVarun Wadekar 2094c672e7SVarun Wadekar /******************************************************************************* 2194c672e7SVarun Wadekar * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 2294c672e7SVarun Wadekar * call as the `state-id` field in the 'power state' parameter. 2394c672e7SVarun Wadekar ******************************************************************************/ 2494c672e7SVarun Wadekar #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN 2594c672e7SVarun Wadekar 2694c672e7SVarun Wadekar /******************************************************************************* 279f9bafa3SVarun Wadekar * Platform power states (used by PSCI framework) 289f9bafa3SVarun Wadekar * 299f9bafa3SVarun Wadekar * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 309f9bafa3SVarun Wadekar * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 319f9bafa3SVarun Wadekar ******************************************************************************/ 32*70cb692eSVarun Wadekar #define PLAT_MAX_RET_STATE U(1) 33*70cb692eSVarun Wadekar #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) 349f9bafa3SVarun Wadekar 359f9bafa3SVarun Wadekar /******************************************************************************* 3608438e24SVarun Wadekar * GIC memory map 3708438e24SVarun Wadekar ******************************************************************************/ 38*70cb692eSVarun Wadekar #define TEGRA_GICD_BASE U(0x50041000) 39*70cb692eSVarun Wadekar #define TEGRA_GICC_BASE U(0x50042000) 4008438e24SVarun Wadekar 4108438e24SVarun Wadekar /******************************************************************************* 4242ca2d86SVarun Wadekar * Tegra Memory Select Switch Controller constants 4342ca2d86SVarun Wadekar ******************************************************************************/ 44*70cb692eSVarun Wadekar #define TEGRA_MSELECT_BASE U(0x50060000) 4542ca2d86SVarun Wadekar 46*70cb692eSVarun Wadekar #define MSELECT_CONFIG U(0x0) 47*70cb692eSVarun Wadekar #define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29)) 48*70cb692eSVarun Wadekar #define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28)) 49*70cb692eSVarun Wadekar #define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27)) 50*70cb692eSVarun Wadekar #define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25)) 51*70cb692eSVarun Wadekar #define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24)) 5242ca2d86SVarun Wadekar #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ 5342ca2d86SVarun Wadekar UNSUPPORTED_TX_ERR_MASTER1_BIT) 5442ca2d86SVarun Wadekar #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ 5542ca2d86SVarun Wadekar ENABLE_WRAP_INCR_MASTER1_BIT | \ 5642ca2d86SVarun Wadekar ENABLE_WRAP_INCR_MASTER0_BIT) 5742ca2d86SVarun Wadekar 5842ca2d86SVarun Wadekar /******************************************************************************* 5908438e24SVarun Wadekar * Tegra micro-seconds timer constants 6008438e24SVarun Wadekar ******************************************************************************/ 61*70cb692eSVarun Wadekar #define TEGRA_TMRUS_BASE U(0x60005010) 62*70cb692eSVarun Wadekar #define TEGRA_TMRUS_SIZE U(0x1000) 6308438e24SVarun Wadekar 6408438e24SVarun Wadekar /******************************************************************************* 6508438e24SVarun Wadekar * Tegra Clock and Reset Controller constants 6608438e24SVarun Wadekar ******************************************************************************/ 67*70cb692eSVarun Wadekar #define TEGRA_CAR_RESET_BASE U(0x60006000) 6808438e24SVarun Wadekar 6908438e24SVarun Wadekar /******************************************************************************* 7008438e24SVarun Wadekar * Tegra Flow Controller constants 7108438e24SVarun Wadekar ******************************************************************************/ 72*70cb692eSVarun Wadekar #define TEGRA_FLOWCTRL_BASE U(0x60007000) 7308438e24SVarun Wadekar 7408438e24SVarun Wadekar /******************************************************************************* 7508438e24SVarun Wadekar * Tegra Secure Boot Controller constants 7608438e24SVarun Wadekar ******************************************************************************/ 77*70cb692eSVarun Wadekar #define TEGRA_SB_BASE U(0x6000C200) 7808438e24SVarun Wadekar 7908438e24SVarun Wadekar /******************************************************************************* 8008438e24SVarun Wadekar * Tegra Exception Vectors constants 8108438e24SVarun Wadekar ******************************************************************************/ 82*70cb692eSVarun Wadekar #define TEGRA_EVP_BASE U(0x6000F000) 8308438e24SVarun Wadekar 8408438e24SVarun Wadekar /******************************************************************************* 85e954ab8fSVarun Wadekar * Tegra Miscellaneous register constants 86e954ab8fSVarun Wadekar ******************************************************************************/ 87*70cb692eSVarun Wadekar #define TEGRA_MISC_BASE U(0x70000000) 88*70cb692eSVarun Wadekar #define HARDWARE_REVISION_OFFSET U(0x804) 89e954ab8fSVarun Wadekar 90e954ab8fSVarun Wadekar /******************************************************************************* 91e1084216SVarun Wadekar * Tegra UART controller base addresses 92e1084216SVarun Wadekar ******************************************************************************/ 93*70cb692eSVarun Wadekar #define TEGRA_UARTA_BASE U(0x70006000) 94*70cb692eSVarun Wadekar #define TEGRA_UARTB_BASE U(0x70006040) 95*70cb692eSVarun Wadekar #define TEGRA_UARTC_BASE U(0x70006200) 96*70cb692eSVarun Wadekar #define TEGRA_UARTD_BASE U(0x70006300) 97*70cb692eSVarun Wadekar #define TEGRA_UARTE_BASE U(0x70006400) 98e1084216SVarun Wadekar 99e1084216SVarun Wadekar /******************************************************************************* 10008438e24SVarun Wadekar * Tegra Power Mgmt Controller constants 10108438e24SVarun Wadekar ******************************************************************************/ 102*70cb692eSVarun Wadekar #define TEGRA_PMC_BASE U(0x7000E400) 10308438e24SVarun Wadekar 10408438e24SVarun Wadekar /******************************************************************************* 10508438e24SVarun Wadekar * Tegra Memory Controller constants 10608438e24SVarun Wadekar ******************************************************************************/ 107*70cb692eSVarun Wadekar #define TEGRA_MC_BASE U(0x70019000) 10808438e24SVarun Wadekar 1090258840eSVarun Wadekar /* TZDRAM carveout configuration registers */ 110*70cb692eSVarun Wadekar #define MC_SECURITY_CFG0_0 U(0x70) 111*70cb692eSVarun Wadekar #define MC_SECURITY_CFG1_0 U(0x74) 112*70cb692eSVarun Wadekar #define MC_SECURITY_CFG3_0 U(0x9BC) 1130258840eSVarun Wadekar 1140258840eSVarun Wadekar /* Video Memory carveout configuration registers */ 115*70cb692eSVarun Wadekar #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 116*70cb692eSVarun Wadekar #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 117*70cb692eSVarun Wadekar #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) 1180258840eSVarun Wadekar 11906b19d58SVarun Wadekar /******************************************************************************* 12006b19d58SVarun Wadekar * Tegra TZRAM constants 12106b19d58SVarun Wadekar ******************************************************************************/ 122*70cb692eSVarun Wadekar #define TEGRA_TZRAM_BASE U(0x7C010000) 123*70cb692eSVarun Wadekar #define TEGRA_TZRAM_SIZE U(0x10000) 12406b19d58SVarun Wadekar 12508438e24SVarun Wadekar #endif /* __TEGRA_DEF_H__ */ 126