108438e24SVarun Wadekar /* 2e99eeec6SSteven Kao * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 7c3cf06f1SAntonio Nino Diaz #ifndef TEGRA_DEF_H 8c3cf06f1SAntonio Nino Diaz #define TEGRA_DEF_H 908438e24SVarun Wadekar 1009d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 1170cb692eSVarun Wadekar 1208438e24SVarun Wadekar /******************************************************************************* 1394c672e7SVarun Wadekar * Power down state IDs 1494c672e7SVarun Wadekar ******************************************************************************/ 1570cb692eSVarun Wadekar #define PSTATE_ID_CORE_POWERDN U(7) 1670cb692eSVarun Wadekar #define PSTATE_ID_CLUSTER_IDLE U(16) 1770cb692eSVarun Wadekar #define PSTATE_ID_CLUSTER_POWERDN U(17) 1870cb692eSVarun Wadekar #define PSTATE_ID_SOC_POWERDN U(27) 1994c672e7SVarun Wadekar 2094c672e7SVarun Wadekar /******************************************************************************* 2194c672e7SVarun Wadekar * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 2294c672e7SVarun Wadekar * call as the `state-id` field in the 'power state' parameter. 2394c672e7SVarun Wadekar ******************************************************************************/ 2494c672e7SVarun Wadekar #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN 2594c672e7SVarun Wadekar 2694c672e7SVarun Wadekar /******************************************************************************* 279f9bafa3SVarun Wadekar * Platform power states (used by PSCI framework) 289f9bafa3SVarun Wadekar * 299f9bafa3SVarun Wadekar * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 309f9bafa3SVarun Wadekar * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 319f9bafa3SVarun Wadekar ******************************************************************************/ 3270cb692eSVarun Wadekar #define PLAT_MAX_RET_STATE U(1) 3370cb692eSVarun Wadekar #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) 349f9bafa3SVarun Wadekar 359f9bafa3SVarun Wadekar /******************************************************************************* 36dd1a71f1SVarun Wadekar * iRAM memory constants 37dd1a71f1SVarun Wadekar ******************************************************************************/ 38223844afSVarun Wadekar #define TEGRA_IRAM_BASE 0x40000000 39dd1a71f1SVarun Wadekar 40dd1a71f1SVarun Wadekar /******************************************************************************* 4108438e24SVarun Wadekar * GIC memory map 4208438e24SVarun Wadekar ******************************************************************************/ 4370cb692eSVarun Wadekar #define TEGRA_GICD_BASE U(0x50041000) 4470cb692eSVarun Wadekar #define TEGRA_GICC_BASE U(0x50042000) 4508438e24SVarun Wadekar 4608438e24SVarun Wadekar /******************************************************************************* 4742ca2d86SVarun Wadekar * Tegra Memory Select Switch Controller constants 4842ca2d86SVarun Wadekar ******************************************************************************/ 4970cb692eSVarun Wadekar #define TEGRA_MSELECT_BASE U(0x50060000) 5042ca2d86SVarun Wadekar 5170cb692eSVarun Wadekar #define MSELECT_CONFIG U(0x0) 5270cb692eSVarun Wadekar #define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29)) 5370cb692eSVarun Wadekar #define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28)) 5470cb692eSVarun Wadekar #define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27)) 5570cb692eSVarun Wadekar #define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25)) 5670cb692eSVarun Wadekar #define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24)) 5742ca2d86SVarun Wadekar #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ 5842ca2d86SVarun Wadekar UNSUPPORTED_TX_ERR_MASTER1_BIT) 5942ca2d86SVarun Wadekar #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ 6042ca2d86SVarun Wadekar ENABLE_WRAP_INCR_MASTER1_BIT | \ 6142ca2d86SVarun Wadekar ENABLE_WRAP_INCR_MASTER0_BIT) 6242ca2d86SVarun Wadekar 6342ca2d86SVarun Wadekar /******************************************************************************* 64dd1a71f1SVarun Wadekar * Tegra Resource Semaphore constants 65dd1a71f1SVarun Wadekar ******************************************************************************/ 66dd1a71f1SVarun Wadekar #define TEGRA_RES_SEMA_BASE 0x60001000UL 67dd1a71f1SVarun Wadekar #define STA_OFFSET 0UL 68dd1a71f1SVarun Wadekar #define SET_OFFSET 4UL 69dd1a71f1SVarun Wadekar #define CLR_OFFSET 8UL 70dd1a71f1SVarun Wadekar 71dd1a71f1SVarun Wadekar /******************************************************************************* 72dd1a71f1SVarun Wadekar * Tegra Primary Interrupt Controller constants 73dd1a71f1SVarun Wadekar ******************************************************************************/ 74dd1a71f1SVarun Wadekar #define TEGRA_PRI_ICTLR_BASE 0x60004000UL 75dd1a71f1SVarun Wadekar #define CPU_IEP_FIR_SET 0x18UL 76dd1a71f1SVarun Wadekar 77dd1a71f1SVarun Wadekar /******************************************************************************* 7808438e24SVarun Wadekar * Tegra micro-seconds timer constants 7908438e24SVarun Wadekar ******************************************************************************/ 8070cb692eSVarun Wadekar #define TEGRA_TMRUS_BASE U(0x60005010) 8170cb692eSVarun Wadekar #define TEGRA_TMRUS_SIZE U(0x1000) 8208438e24SVarun Wadekar 8308438e24SVarun Wadekar /******************************************************************************* 8408438e24SVarun Wadekar * Tegra Clock and Reset Controller constants 8508438e24SVarun Wadekar ******************************************************************************/ 8670cb692eSVarun Wadekar #define TEGRA_CAR_RESET_BASE U(0x60006000) 87f5f64e4dSVarun Wadekar #define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) 88f5f64e4dSVarun Wadekar #define GPU_RESET_BIT (U(1) << 24) 89dd1a71f1SVarun Wadekar #define TEGRA_RST_DEV_CLR_V U(0x434) 90dd1a71f1SVarun Wadekar #define TEGRA_CLK_ENB_V U(0x440) 9108438e24SVarun Wadekar 9299359f1dSSamuel Payne /* SE Clock Offsets */ 9399359f1dSSamuel Payne #define TEGRA_RST_DEVICES_V 0x358UL 9499359f1dSSamuel Payne #define SE_RESET_BIT (0x1UL << 31) 9599359f1dSSamuel Payne #define TEGRA_RST_DEVICES_W 0x35CUL 9699359f1dSSamuel Payne #define ENTROPY_CLK_ENB_BIT (0x1UL << 21) 9799359f1dSSamuel Payne #define TEGRA_CLK_OUT_ENB_V 0x360UL 9899359f1dSSamuel Payne #define SE_CLK_ENB_BIT (0x1UL << 31) 9999359f1dSSamuel Payne #define TEGRA_CLK_OUT_ENB_W 0x364UL 10099359f1dSSamuel Payne #define ENTROPY_RESET_BIT (0x1UL << 21) 10199359f1dSSamuel Payne 10208438e24SVarun Wadekar /******************************************************************************* 10308438e24SVarun Wadekar * Tegra Flow Controller constants 10408438e24SVarun Wadekar ******************************************************************************/ 10570cb692eSVarun Wadekar #define TEGRA_FLOWCTRL_BASE U(0x60007000) 10608438e24SVarun Wadekar 10708438e24SVarun Wadekar /******************************************************************************* 108ce3c97c9SMarvin Hsu * Tegra AHB arbitration controller 109ce3c97c9SMarvin Hsu ******************************************************************************/ 110ce3c97c9SMarvin Hsu #define TEGRA_AHB_ARB_BASE 0x6000C000UL 111ce3c97c9SMarvin Hsu 112ce3c97c9SMarvin Hsu /******************************************************************************* 11308438e24SVarun Wadekar * Tegra Secure Boot Controller constants 11408438e24SVarun Wadekar ******************************************************************************/ 11570cb692eSVarun Wadekar #define TEGRA_SB_BASE U(0x6000C200) 11608438e24SVarun Wadekar 11708438e24SVarun Wadekar /******************************************************************************* 11808438e24SVarun Wadekar * Tegra Exception Vectors constants 11908438e24SVarun Wadekar ******************************************************************************/ 12070cb692eSVarun Wadekar #define TEGRA_EVP_BASE U(0x6000F000) 12108438e24SVarun Wadekar 12208438e24SVarun Wadekar /******************************************************************************* 123e954ab8fSVarun Wadekar * Tegra Miscellaneous register constants 124e954ab8fSVarun Wadekar ******************************************************************************/ 12570cb692eSVarun Wadekar #define TEGRA_MISC_BASE U(0x70000000) 12670cb692eSVarun Wadekar #define HARDWARE_REVISION_OFFSET U(0x804) 127e954ab8fSVarun Wadekar 128e954ab8fSVarun Wadekar /******************************************************************************* 129e1084216SVarun Wadekar * Tegra UART controller base addresses 130e1084216SVarun Wadekar ******************************************************************************/ 13170cb692eSVarun Wadekar #define TEGRA_UARTA_BASE U(0x70006000) 13270cb692eSVarun Wadekar #define TEGRA_UARTB_BASE U(0x70006040) 13370cb692eSVarun Wadekar #define TEGRA_UARTC_BASE U(0x70006200) 13470cb692eSVarun Wadekar #define TEGRA_UARTD_BASE U(0x70006300) 13570cb692eSVarun Wadekar #define TEGRA_UARTE_BASE U(0x70006400) 136e1084216SVarun Wadekar 137e1084216SVarun Wadekar /******************************************************************************* 1385ed1755aSMarvin Hsu * Tegra Fuse Controller related constants 1395ed1755aSMarvin Hsu ******************************************************************************/ 1405ed1755aSMarvin Hsu #define TEGRA_FUSE_BASE 0x7000F800UL 1415ed1755aSMarvin Hsu #define FUSE_BOOT_SECURITY_INFO 0x268UL 1425ed1755aSMarvin Hsu #define FUSE_ATOMIC_SAVE_CARVEOUT_EN (0x1U << 7) 143620b2233SSamuel Payne #define FUSE_JTAG_SECUREID_VALID (0x104UL) 144620b2233SSamuel Payne #define ECID_VALID (0x1UL) 1455ed1755aSMarvin Hsu 1465ed1755aSMarvin Hsu 1475ed1755aSMarvin Hsu /******************************************************************************* 14808438e24SVarun Wadekar * Tegra Power Mgmt Controller constants 14908438e24SVarun Wadekar ******************************************************************************/ 15070cb692eSVarun Wadekar #define TEGRA_PMC_BASE U(0x7000E400) 15108438e24SVarun Wadekar 15208438e24SVarun Wadekar /******************************************************************************* 153dd1a71f1SVarun Wadekar * Tegra Atomics constants 154dd1a71f1SVarun Wadekar ******************************************************************************/ 155dd1a71f1SVarun Wadekar #define TEGRA_ATOMICS_BASE 0x70016000UL 156dd1a71f1SVarun Wadekar #define TRIGGER0_REG_OFFSET 0UL 157dd1a71f1SVarun Wadekar #define TRIGGER_WIDTH_SHIFT 4UL 158dd1a71f1SVarun Wadekar #define TRIGGER_ID_SHIFT 16UL 159dd1a71f1SVarun Wadekar #define RESULT0_REG_OFFSET 0xC00UL 160dd1a71f1SVarun Wadekar 161dd1a71f1SVarun Wadekar /******************************************************************************* 16208438e24SVarun Wadekar * Tegra Memory Controller constants 16308438e24SVarun Wadekar ******************************************************************************/ 16470cb692eSVarun Wadekar #define TEGRA_MC_BASE U(0x70019000) 16508438e24SVarun Wadekar 166*650d9c52SHarvey Hsieh /* Memory Controller Interrupt Status */ 167*650d9c52SHarvey Hsieh #define MC_INTSTATUS 0x00U 168*650d9c52SHarvey Hsieh 1690258840eSVarun Wadekar /* TZDRAM carveout configuration registers */ 17070cb692eSVarun Wadekar #define MC_SECURITY_CFG0_0 U(0x70) 17170cb692eSVarun Wadekar #define MC_SECURITY_CFG1_0 U(0x74) 17270cb692eSVarun Wadekar #define MC_SECURITY_CFG3_0 U(0x9BC) 1730258840eSVarun Wadekar 1740258840eSVarun Wadekar /* Video Memory carveout configuration registers */ 17570cb692eSVarun Wadekar #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 17670cb692eSVarun Wadekar #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 17770cb692eSVarun Wadekar #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) 1780258840eSVarun Wadekar 17986d0a52bSSamuel Payne /* SMMU configuration registers*/ 180aa64c5fbSAnthony Zhou #define MC_SMMU_PPCS_ASID_0 0x270U 18186d0a52bSSamuel Payne #define PPCS_SMMU_ENABLE (0x1U << 31) 18286d0a52bSSamuel Payne 18306b19d58SVarun Wadekar /******************************************************************************* 184ce3c97c9SMarvin Hsu * Tegra SE constants 185ce3c97c9SMarvin Hsu ******************************************************************************/ 186ce3c97c9SMarvin Hsu #define TEGRA_SE1_BASE U(0x70012000) 187ce3c97c9SMarvin Hsu #define TEGRA_SE2_BASE U(0x70412000) 188ce3c97c9SMarvin Hsu #define TEGRA_PKA1_BASE U(0x70420000) 189ce3c97c9SMarvin Hsu #define TEGRA_SE2_RANGE_SIZE U(0x2000) 190ce3c97c9SMarvin Hsu #define SE_TZRAM_SECURITY U(0x4) 191ce3c97c9SMarvin Hsu 192ce3c97c9SMarvin Hsu /******************************************************************************* 19306b19d58SVarun Wadekar * Tegra TZRAM constants 19406b19d58SVarun Wadekar ******************************************************************************/ 19570cb692eSVarun Wadekar #define TEGRA_TZRAM_BASE U(0x7C010000) 19670cb692eSVarun Wadekar #define TEGRA_TZRAM_SIZE U(0x10000) 19706b19d58SVarun Wadekar 1985ed1755aSMarvin Hsu /******************************************************************************* 1995ed1755aSMarvin Hsu * Tegra TZRAM carveout constants 2005ed1755aSMarvin Hsu ******************************************************************************/ 2015ed1755aSMarvin Hsu #define TEGRA_TZRAM_CARVEOUT_BASE U(0x7C04C000) 2025ed1755aSMarvin Hsu #define TEGRA_TZRAM_CARVEOUT_SIZE U(0x4000) 2035ed1755aSMarvin Hsu 204c3cf06f1SAntonio Nino Diaz #endif /* TEGRA_DEF_H */ 205