108438e24SVarun Wadekar /* 2*51a5e593SVarun Wadekar * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 7c3cf06f1SAntonio Nino Diaz #ifndef TEGRA_DEF_H 8c3cf06f1SAntonio Nino Diaz #define TEGRA_DEF_H 908438e24SVarun Wadekar 1009d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 1170cb692eSVarun Wadekar 1208438e24SVarun Wadekar /******************************************************************************* 1394c672e7SVarun Wadekar * Power down state IDs 1494c672e7SVarun Wadekar ******************************************************************************/ 1570cb692eSVarun Wadekar #define PSTATE_ID_CORE_POWERDN U(7) 1670cb692eSVarun Wadekar #define PSTATE_ID_CLUSTER_IDLE U(16) 1770cb692eSVarun Wadekar #define PSTATE_ID_CLUSTER_POWERDN U(17) 1870cb692eSVarun Wadekar #define PSTATE_ID_SOC_POWERDN U(27) 1994c672e7SVarun Wadekar 2094c672e7SVarun Wadekar /******************************************************************************* 2194c672e7SVarun Wadekar * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 2294c672e7SVarun Wadekar * call as the `state-id` field in the 'power state' parameter. 2394c672e7SVarun Wadekar ******************************************************************************/ 2494c672e7SVarun Wadekar #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN 2594c672e7SVarun Wadekar 2694c672e7SVarun Wadekar /******************************************************************************* 279f9bafa3SVarun Wadekar * Platform power states (used by PSCI framework) 289f9bafa3SVarun Wadekar * 299f9bafa3SVarun Wadekar * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 309f9bafa3SVarun Wadekar * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 319f9bafa3SVarun Wadekar ******************************************************************************/ 3270cb692eSVarun Wadekar #define PLAT_MAX_RET_STATE U(1) 3370cb692eSVarun Wadekar #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) 349f9bafa3SVarun Wadekar 359f9bafa3SVarun Wadekar /******************************************************************************* 36dd1a71f1SVarun Wadekar * iRAM memory constants 37dd1a71f1SVarun Wadekar ******************************************************************************/ 38223844afSVarun Wadekar #define TEGRA_IRAM_BASE 0x40000000 39dd1a71f1SVarun Wadekar 40dd1a71f1SVarun Wadekar /******************************************************************************* 4108438e24SVarun Wadekar * GIC memory map 4208438e24SVarun Wadekar ******************************************************************************/ 4370cb692eSVarun Wadekar #define TEGRA_GICD_BASE U(0x50041000) 4470cb692eSVarun Wadekar #define TEGRA_GICC_BASE U(0x50042000) 4508438e24SVarun Wadekar 4608438e24SVarun Wadekar /******************************************************************************* 47*51a5e593SVarun Wadekar * Secure IRQ definitions 48*51a5e593SVarun Wadekar ******************************************************************************/ 49*51a5e593SVarun Wadekar #define TEGRA210_WDT_CPU_LEGACY_FIQ U(28) 50*51a5e593SVarun Wadekar 51*51a5e593SVarun Wadekar /******************************************************************************* 5242ca2d86SVarun Wadekar * Tegra Memory Select Switch Controller constants 5342ca2d86SVarun Wadekar ******************************************************************************/ 5470cb692eSVarun Wadekar #define TEGRA_MSELECT_BASE U(0x50060000) 5542ca2d86SVarun Wadekar 5670cb692eSVarun Wadekar #define MSELECT_CONFIG U(0x0) 5770cb692eSVarun Wadekar #define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29)) 5870cb692eSVarun Wadekar #define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28)) 5970cb692eSVarun Wadekar #define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27)) 6070cb692eSVarun Wadekar #define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25)) 6170cb692eSVarun Wadekar #define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24)) 6242ca2d86SVarun Wadekar #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ 6342ca2d86SVarun Wadekar UNSUPPORTED_TX_ERR_MASTER1_BIT) 6442ca2d86SVarun Wadekar #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ 6542ca2d86SVarun Wadekar ENABLE_WRAP_INCR_MASTER1_BIT | \ 6642ca2d86SVarun Wadekar ENABLE_WRAP_INCR_MASTER0_BIT) 6742ca2d86SVarun Wadekar 6842ca2d86SVarun Wadekar /******************************************************************************* 69dd1a71f1SVarun Wadekar * Tegra Resource Semaphore constants 70dd1a71f1SVarun Wadekar ******************************************************************************/ 71dd1a71f1SVarun Wadekar #define TEGRA_RES_SEMA_BASE 0x60001000UL 72dd1a71f1SVarun Wadekar #define STA_OFFSET 0UL 73dd1a71f1SVarun Wadekar #define SET_OFFSET 4UL 74dd1a71f1SVarun Wadekar #define CLR_OFFSET 8UL 75dd1a71f1SVarun Wadekar 76dd1a71f1SVarun Wadekar /******************************************************************************* 77dd1a71f1SVarun Wadekar * Tegra Primary Interrupt Controller constants 78dd1a71f1SVarun Wadekar ******************************************************************************/ 79dd1a71f1SVarun Wadekar #define TEGRA_PRI_ICTLR_BASE 0x60004000UL 80dd1a71f1SVarun Wadekar #define CPU_IEP_FIR_SET 0x18UL 81dd1a71f1SVarun Wadekar 82dd1a71f1SVarun Wadekar /******************************************************************************* 8308438e24SVarun Wadekar * Tegra micro-seconds timer constants 8408438e24SVarun Wadekar ******************************************************************************/ 8570cb692eSVarun Wadekar #define TEGRA_TMRUS_BASE U(0x60005010) 8670cb692eSVarun Wadekar #define TEGRA_TMRUS_SIZE U(0x1000) 8708438e24SVarun Wadekar 8808438e24SVarun Wadekar /******************************************************************************* 8908438e24SVarun Wadekar * Tegra Clock and Reset Controller constants 9008438e24SVarun Wadekar ******************************************************************************/ 9170cb692eSVarun Wadekar #define TEGRA_CAR_RESET_BASE U(0x60006000) 92f5f64e4dSVarun Wadekar #define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) 933e28e935SJeetesh Burman #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290) 94f5f64e4dSVarun Wadekar #define GPU_RESET_BIT (U(1) << 24) 953e28e935SJeetesh Burman #define GPU_SET_BIT (U(1) << 24) 96dd1a71f1SVarun Wadekar #define TEGRA_RST_DEV_CLR_V U(0x434) 97dd1a71f1SVarun Wadekar #define TEGRA_CLK_ENB_V U(0x440) 9808438e24SVarun Wadekar 9999359f1dSSamuel Payne /* SE Clock Offsets */ 10099359f1dSSamuel Payne #define TEGRA_RST_DEVICES_V 0x358UL 10199359f1dSSamuel Payne #define SE_RESET_BIT (0x1UL << 31) 10299359f1dSSamuel Payne #define TEGRA_RST_DEVICES_W 0x35CUL 10399359f1dSSamuel Payne #define ENTROPY_CLK_ENB_BIT (0x1UL << 21) 10499359f1dSSamuel Payne #define TEGRA_CLK_OUT_ENB_V 0x360UL 10599359f1dSSamuel Payne #define SE_CLK_ENB_BIT (0x1UL << 31) 10699359f1dSSamuel Payne #define TEGRA_CLK_OUT_ENB_W 0x364UL 10799359f1dSSamuel Payne #define ENTROPY_RESET_BIT (0x1UL << 21) 10899359f1dSSamuel Payne 10908438e24SVarun Wadekar /******************************************************************************* 11008438e24SVarun Wadekar * Tegra Flow Controller constants 11108438e24SVarun Wadekar ******************************************************************************/ 11270cb692eSVarun Wadekar #define TEGRA_FLOWCTRL_BASE U(0x60007000) 11308438e24SVarun Wadekar 11408438e24SVarun Wadekar /******************************************************************************* 115ce3c97c9SMarvin Hsu * Tegra AHB arbitration controller 116ce3c97c9SMarvin Hsu ******************************************************************************/ 117ce3c97c9SMarvin Hsu #define TEGRA_AHB_ARB_BASE 0x6000C000UL 118ce3c97c9SMarvin Hsu 119ce3c97c9SMarvin Hsu /******************************************************************************* 12008438e24SVarun Wadekar * Tegra Secure Boot Controller constants 12108438e24SVarun Wadekar ******************************************************************************/ 12270cb692eSVarun Wadekar #define TEGRA_SB_BASE U(0x6000C200) 12308438e24SVarun Wadekar 12408438e24SVarun Wadekar /******************************************************************************* 12508438e24SVarun Wadekar * Tegra Exception Vectors constants 12608438e24SVarun Wadekar ******************************************************************************/ 12770cb692eSVarun Wadekar #define TEGRA_EVP_BASE U(0x6000F000) 12808438e24SVarun Wadekar 12908438e24SVarun Wadekar /******************************************************************************* 130e954ab8fSVarun Wadekar * Tegra Miscellaneous register constants 131e954ab8fSVarun Wadekar ******************************************************************************/ 13270cb692eSVarun Wadekar #define TEGRA_MISC_BASE U(0x70000000) 13370cb692eSVarun Wadekar #define HARDWARE_REVISION_OFFSET U(0x804) 134e954ab8fSVarun Wadekar 135e954ab8fSVarun Wadekar /******************************************************************************* 136e1084216SVarun Wadekar * Tegra UART controller base addresses 137e1084216SVarun Wadekar ******************************************************************************/ 13870cb692eSVarun Wadekar #define TEGRA_UARTA_BASE U(0x70006000) 13970cb692eSVarun Wadekar #define TEGRA_UARTB_BASE U(0x70006040) 14070cb692eSVarun Wadekar #define TEGRA_UARTC_BASE U(0x70006200) 14170cb692eSVarun Wadekar #define TEGRA_UARTD_BASE U(0x70006300) 14270cb692eSVarun Wadekar #define TEGRA_UARTE_BASE U(0x70006400) 143e1084216SVarun Wadekar 144e1084216SVarun Wadekar /******************************************************************************* 1455ed1755aSMarvin Hsu * Tegra Fuse Controller related constants 1465ed1755aSMarvin Hsu ******************************************************************************/ 1475ed1755aSMarvin Hsu #define TEGRA_FUSE_BASE 0x7000F800UL 1485ed1755aSMarvin Hsu #define FUSE_BOOT_SECURITY_INFO 0x268UL 1495ed1755aSMarvin Hsu #define FUSE_ATOMIC_SAVE_CARVEOUT_EN (0x1U << 7) 150620b2233SSamuel Payne #define FUSE_JTAG_SECUREID_VALID (0x104UL) 151620b2233SSamuel Payne #define ECID_VALID (0x1UL) 1525ed1755aSMarvin Hsu 1535ed1755aSMarvin Hsu 1545ed1755aSMarvin Hsu /******************************************************************************* 15508438e24SVarun Wadekar * Tegra Power Mgmt Controller constants 15608438e24SVarun Wadekar ******************************************************************************/ 15770cb692eSVarun Wadekar #define TEGRA_PMC_BASE U(0x7000E400) 15808438e24SVarun Wadekar 15908438e24SVarun Wadekar /******************************************************************************* 160dd1a71f1SVarun Wadekar * Tegra Atomics constants 161dd1a71f1SVarun Wadekar ******************************************************************************/ 162dd1a71f1SVarun Wadekar #define TEGRA_ATOMICS_BASE 0x70016000UL 163dd1a71f1SVarun Wadekar #define TRIGGER0_REG_OFFSET 0UL 164dd1a71f1SVarun Wadekar #define TRIGGER_WIDTH_SHIFT 4UL 165dd1a71f1SVarun Wadekar #define TRIGGER_ID_SHIFT 16UL 166dd1a71f1SVarun Wadekar #define RESULT0_REG_OFFSET 0xC00UL 167dd1a71f1SVarun Wadekar 168dd1a71f1SVarun Wadekar /******************************************************************************* 16908438e24SVarun Wadekar * Tegra Memory Controller constants 17008438e24SVarun Wadekar ******************************************************************************/ 17170cb692eSVarun Wadekar #define TEGRA_MC_BASE U(0x70019000) 17208438e24SVarun Wadekar 173650d9c52SHarvey Hsieh /* Memory Controller Interrupt Status */ 174650d9c52SHarvey Hsieh #define MC_INTSTATUS 0x00U 175650d9c52SHarvey Hsieh 1760258840eSVarun Wadekar /* TZDRAM carveout configuration registers */ 17770cb692eSVarun Wadekar #define MC_SECURITY_CFG0_0 U(0x70) 17870cb692eSVarun Wadekar #define MC_SECURITY_CFG1_0 U(0x74) 17970cb692eSVarun Wadekar #define MC_SECURITY_CFG3_0 U(0x9BC) 1800258840eSVarun Wadekar 1810258840eSVarun Wadekar /* Video Memory carveout configuration registers */ 18270cb692eSVarun Wadekar #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 18370cb692eSVarun Wadekar #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 18470cb692eSVarun Wadekar #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) 1850258840eSVarun Wadekar 18686d0a52bSSamuel Payne /* SMMU configuration registers*/ 187aa64c5fbSAnthony Zhou #define MC_SMMU_PPCS_ASID_0 0x270U 18886d0a52bSSamuel Payne #define PPCS_SMMU_ENABLE (0x1U << 31) 18986d0a52bSSamuel Payne 19006b19d58SVarun Wadekar /******************************************************************************* 191ce3c97c9SMarvin Hsu * Tegra SE constants 192ce3c97c9SMarvin Hsu ******************************************************************************/ 193ce3c97c9SMarvin Hsu #define TEGRA_SE1_BASE U(0x70012000) 194ce3c97c9SMarvin Hsu #define TEGRA_SE2_BASE U(0x70412000) 195ce3c97c9SMarvin Hsu #define TEGRA_PKA1_BASE U(0x70420000) 196ce3c97c9SMarvin Hsu #define TEGRA_SE2_RANGE_SIZE U(0x2000) 197ce3c97c9SMarvin Hsu #define SE_TZRAM_SECURITY U(0x4) 198ce3c97c9SMarvin Hsu 199ce3c97c9SMarvin Hsu /******************************************************************************* 20006b19d58SVarun Wadekar * Tegra TZRAM constants 20106b19d58SVarun Wadekar ******************************************************************************/ 20270cb692eSVarun Wadekar #define TEGRA_TZRAM_BASE U(0x7C010000) 20370cb692eSVarun Wadekar #define TEGRA_TZRAM_SIZE U(0x10000) 20406b19d58SVarun Wadekar 2055ed1755aSMarvin Hsu /******************************************************************************* 2065ed1755aSMarvin Hsu * Tegra TZRAM carveout constants 2075ed1755aSMarvin Hsu ******************************************************************************/ 2085ed1755aSMarvin Hsu #define TEGRA_TZRAM_CARVEOUT_BASE U(0x7C04C000) 2095ed1755aSMarvin Hsu #define TEGRA_TZRAM_CARVEOUT_SIZE U(0x4000) 2105ed1755aSMarvin Hsu 211c3cf06f1SAntonio Nino Diaz #endif /* TEGRA_DEF_H */ 212