108438e24SVarun Wadekar /* 251a5e593SVarun Wadekar * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 7c3cf06f1SAntonio Nino Diaz #ifndef TEGRA_DEF_H 8c3cf06f1SAntonio Nino Diaz #define TEGRA_DEF_H 908438e24SVarun Wadekar 1009d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 1170cb692eSVarun Wadekar 1208438e24SVarun Wadekar /******************************************************************************* 1394c672e7SVarun Wadekar * Power down state IDs 1494c672e7SVarun Wadekar ******************************************************************************/ 1570cb692eSVarun Wadekar #define PSTATE_ID_CORE_POWERDN U(7) 1670cb692eSVarun Wadekar #define PSTATE_ID_CLUSTER_IDLE U(16) 1770cb692eSVarun Wadekar #define PSTATE_ID_SOC_POWERDN U(27) 1894c672e7SVarun Wadekar 1994c672e7SVarun Wadekar /******************************************************************************* 2094c672e7SVarun Wadekar * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 2194c672e7SVarun Wadekar * call as the `state-id` field in the 'power state' parameter. 2294c672e7SVarun Wadekar ******************************************************************************/ 2394c672e7SVarun Wadekar #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN 2494c672e7SVarun Wadekar 2594c672e7SVarun Wadekar /******************************************************************************* 269f9bafa3SVarun Wadekar * Platform power states (used by PSCI framework) 279f9bafa3SVarun Wadekar * 289f9bafa3SVarun Wadekar * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 299f9bafa3SVarun Wadekar * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 309f9bafa3SVarun Wadekar ******************************************************************************/ 3170cb692eSVarun Wadekar #define PLAT_MAX_RET_STATE U(1) 3270cb692eSVarun Wadekar #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) 339f9bafa3SVarun Wadekar 349f9bafa3SVarun Wadekar /******************************************************************************* 351d11f73eSSteven Kao * Chip specific page table and MMU setup constants 361d11f73eSSteven Kao ******************************************************************************/ 371d11f73eSSteven Kao #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) 381d11f73eSSteven Kao #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) 391d11f73eSSteven Kao 401d11f73eSSteven Kao /******************************************************************************* 41dd1a71f1SVarun Wadekar * iRAM memory constants 42dd1a71f1SVarun Wadekar ******************************************************************************/ 43*3ca3c27cSVarun Wadekar #define TEGRA_IRAM_BASE U(0x40000000) 44*3ca3c27cSVarun Wadekar #define TEGRA_IRAM_SIZE U(40000) /* 256KB */ 45dd1a71f1SVarun Wadekar 46dd1a71f1SVarun Wadekar /******************************************************************************* 4708438e24SVarun Wadekar * GIC memory map 4808438e24SVarun Wadekar ******************************************************************************/ 4970cb692eSVarun Wadekar #define TEGRA_GICD_BASE U(0x50041000) 5070cb692eSVarun Wadekar #define TEGRA_GICC_BASE U(0x50042000) 5108438e24SVarun Wadekar 5208438e24SVarun Wadekar /******************************************************************************* 5351a5e593SVarun Wadekar * Secure IRQ definitions 5451a5e593SVarun Wadekar ******************************************************************************/ 5551a5e593SVarun Wadekar #define TEGRA210_WDT_CPU_LEGACY_FIQ U(28) 5651a5e593SVarun Wadekar 5751a5e593SVarun Wadekar /******************************************************************************* 5842ca2d86SVarun Wadekar * Tegra Memory Select Switch Controller constants 5942ca2d86SVarun Wadekar ******************************************************************************/ 6070cb692eSVarun Wadekar #define TEGRA_MSELECT_BASE U(0x50060000) 6142ca2d86SVarun Wadekar 6270cb692eSVarun Wadekar #define MSELECT_CONFIG U(0x0) 6370cb692eSVarun Wadekar #define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29)) 6470cb692eSVarun Wadekar #define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28)) 6570cb692eSVarun Wadekar #define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27)) 6670cb692eSVarun Wadekar #define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25)) 6770cb692eSVarun Wadekar #define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24)) 6842ca2d86SVarun Wadekar #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ 6942ca2d86SVarun Wadekar UNSUPPORTED_TX_ERR_MASTER1_BIT) 7042ca2d86SVarun Wadekar #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ 7142ca2d86SVarun Wadekar ENABLE_WRAP_INCR_MASTER1_BIT | \ 7242ca2d86SVarun Wadekar ENABLE_WRAP_INCR_MASTER0_BIT) 7342ca2d86SVarun Wadekar 7442ca2d86SVarun Wadekar /******************************************************************************* 75dd1a71f1SVarun Wadekar * Tegra Resource Semaphore constants 76dd1a71f1SVarun Wadekar ******************************************************************************/ 77dd1a71f1SVarun Wadekar #define TEGRA_RES_SEMA_BASE 0x60001000UL 78dd1a71f1SVarun Wadekar #define STA_OFFSET 0UL 79dd1a71f1SVarun Wadekar #define SET_OFFSET 4UL 80dd1a71f1SVarun Wadekar #define CLR_OFFSET 8UL 81dd1a71f1SVarun Wadekar 82dd1a71f1SVarun Wadekar /******************************************************************************* 83dd1a71f1SVarun Wadekar * Tegra Primary Interrupt Controller constants 84dd1a71f1SVarun Wadekar ******************************************************************************/ 85dd1a71f1SVarun Wadekar #define TEGRA_PRI_ICTLR_BASE 0x60004000UL 86dd1a71f1SVarun Wadekar #define CPU_IEP_FIR_SET 0x18UL 87dd1a71f1SVarun Wadekar 88dd1a71f1SVarun Wadekar /******************************************************************************* 8908438e24SVarun Wadekar * Tegra micro-seconds timer constants 9008438e24SVarun Wadekar ******************************************************************************/ 9170cb692eSVarun Wadekar #define TEGRA_TMRUS_BASE U(0x60005010) 9270cb692eSVarun Wadekar #define TEGRA_TMRUS_SIZE U(0x1000) 9308438e24SVarun Wadekar 9408438e24SVarun Wadekar /******************************************************************************* 9508438e24SVarun Wadekar * Tegra Clock and Reset Controller constants 9608438e24SVarun Wadekar ******************************************************************************/ 9770cb692eSVarun Wadekar #define TEGRA_CAR_RESET_BASE U(0x60006000) 98f5f64e4dSVarun Wadekar #define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) 993e28e935SJeetesh Burman #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290) 100f5f64e4dSVarun Wadekar #define GPU_RESET_BIT (U(1) << 24) 1013e28e935SJeetesh Burman #define GPU_SET_BIT (U(1) << 24) 102dd1a71f1SVarun Wadekar #define TEGRA_RST_DEV_CLR_V U(0x434) 103dd1a71f1SVarun Wadekar #define TEGRA_CLK_ENB_V U(0x440) 10408438e24SVarun Wadekar 10599359f1dSSamuel Payne /* SE Clock Offsets */ 10699359f1dSSamuel Payne #define TEGRA_RST_DEVICES_V 0x358UL 10799359f1dSSamuel Payne #define SE_RESET_BIT (0x1UL << 31) 10899359f1dSSamuel Payne #define TEGRA_RST_DEVICES_W 0x35CUL 10999359f1dSSamuel Payne #define ENTROPY_CLK_ENB_BIT (0x1UL << 21) 11099359f1dSSamuel Payne #define TEGRA_CLK_OUT_ENB_V 0x360UL 11199359f1dSSamuel Payne #define SE_CLK_ENB_BIT (0x1UL << 31) 11299359f1dSSamuel Payne #define TEGRA_CLK_OUT_ENB_W 0x364UL 11399359f1dSSamuel Payne #define ENTROPY_RESET_BIT (0x1UL << 21) 11499359f1dSSamuel Payne 11508438e24SVarun Wadekar /******************************************************************************* 11608438e24SVarun Wadekar * Tegra Flow Controller constants 11708438e24SVarun Wadekar ******************************************************************************/ 11870cb692eSVarun Wadekar #define TEGRA_FLOWCTRL_BASE U(0x60007000) 11908438e24SVarun Wadekar 12008438e24SVarun Wadekar /******************************************************************************* 121ce3c97c9SMarvin Hsu * Tegra AHB arbitration controller 122ce3c97c9SMarvin Hsu ******************************************************************************/ 123ce3c97c9SMarvin Hsu #define TEGRA_AHB_ARB_BASE 0x6000C000UL 124ce3c97c9SMarvin Hsu 125ce3c97c9SMarvin Hsu /******************************************************************************* 12608438e24SVarun Wadekar * Tegra Secure Boot Controller constants 12708438e24SVarun Wadekar ******************************************************************************/ 12870cb692eSVarun Wadekar #define TEGRA_SB_BASE U(0x6000C200) 12908438e24SVarun Wadekar 13008438e24SVarun Wadekar /******************************************************************************* 13108438e24SVarun Wadekar * Tegra Exception Vectors constants 13208438e24SVarun Wadekar ******************************************************************************/ 13370cb692eSVarun Wadekar #define TEGRA_EVP_BASE U(0x6000F000) 13408438e24SVarun Wadekar 13508438e24SVarun Wadekar /******************************************************************************* 136e954ab8fSVarun Wadekar * Tegra Miscellaneous register constants 137e954ab8fSVarun Wadekar ******************************************************************************/ 13870cb692eSVarun Wadekar #define TEGRA_MISC_BASE U(0x70000000) 13970cb692eSVarun Wadekar #define HARDWARE_REVISION_OFFSET U(0x804) 1407db077f2SVarun Wadekar #define PINMUX_AUX_DVFS_PWM U(0x3184) 1417db077f2SVarun Wadekar #define PINMUX_PWM_TRISTATE (U(1) << 4) 142e954ab8fSVarun Wadekar 143e954ab8fSVarun Wadekar /******************************************************************************* 144e1084216SVarun Wadekar * Tegra UART controller base addresses 145e1084216SVarun Wadekar ******************************************************************************/ 14670cb692eSVarun Wadekar #define TEGRA_UARTA_BASE U(0x70006000) 14770cb692eSVarun Wadekar #define TEGRA_UARTB_BASE U(0x70006040) 14870cb692eSVarun Wadekar #define TEGRA_UARTC_BASE U(0x70006200) 14970cb692eSVarun Wadekar #define TEGRA_UARTD_BASE U(0x70006300) 15070cb692eSVarun Wadekar #define TEGRA_UARTE_BASE U(0x70006400) 151e1084216SVarun Wadekar 152e1084216SVarun Wadekar /******************************************************************************* 1535ed1755aSMarvin Hsu * Tegra Fuse Controller related constants 1545ed1755aSMarvin Hsu ******************************************************************************/ 1555ed1755aSMarvin Hsu #define TEGRA_FUSE_BASE 0x7000F800UL 1565ed1755aSMarvin Hsu #define FUSE_BOOT_SECURITY_INFO 0x268UL 1575ed1755aSMarvin Hsu #define FUSE_ATOMIC_SAVE_CARVEOUT_EN (0x1U << 7) 158620b2233SSamuel Payne #define FUSE_JTAG_SECUREID_VALID (0x104UL) 159620b2233SSamuel Payne #define ECID_VALID (0x1UL) 1605ed1755aSMarvin Hsu 1615ed1755aSMarvin Hsu 1625ed1755aSMarvin Hsu /******************************************************************************* 16308438e24SVarun Wadekar * Tegra Power Mgmt Controller constants 16408438e24SVarun Wadekar ******************************************************************************/ 16570cb692eSVarun Wadekar #define TEGRA_PMC_BASE U(0x7000E400) 16608438e24SVarun Wadekar 16708438e24SVarun Wadekar /******************************************************************************* 168dd1a71f1SVarun Wadekar * Tegra Atomics constants 169dd1a71f1SVarun Wadekar ******************************************************************************/ 170dd1a71f1SVarun Wadekar #define TEGRA_ATOMICS_BASE 0x70016000UL 171dd1a71f1SVarun Wadekar #define TRIGGER0_REG_OFFSET 0UL 172dd1a71f1SVarun Wadekar #define TRIGGER_WIDTH_SHIFT 4UL 173dd1a71f1SVarun Wadekar #define TRIGGER_ID_SHIFT 16UL 174dd1a71f1SVarun Wadekar #define RESULT0_REG_OFFSET 0xC00UL 175dd1a71f1SVarun Wadekar 176dd1a71f1SVarun Wadekar /******************************************************************************* 17708438e24SVarun Wadekar * Tegra Memory Controller constants 17808438e24SVarun Wadekar ******************************************************************************/ 17970cb692eSVarun Wadekar #define TEGRA_MC_BASE U(0x70019000) 18008438e24SVarun Wadekar 181650d9c52SHarvey Hsieh /* Memory Controller Interrupt Status */ 182650d9c52SHarvey Hsieh #define MC_INTSTATUS 0x00U 183650d9c52SHarvey Hsieh 1840258840eSVarun Wadekar /* TZDRAM carveout configuration registers */ 18570cb692eSVarun Wadekar #define MC_SECURITY_CFG0_0 U(0x70) 18670cb692eSVarun Wadekar #define MC_SECURITY_CFG1_0 U(0x74) 18770cb692eSVarun Wadekar #define MC_SECURITY_CFG3_0 U(0x9BC) 1880258840eSVarun Wadekar 1890258840eSVarun Wadekar /* Video Memory carveout configuration registers */ 19070cb692eSVarun Wadekar #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 19170cb692eSVarun Wadekar #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 19270cb692eSVarun Wadekar #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) 1930258840eSVarun Wadekar 19486d0a52bSSamuel Payne /* SMMU configuration registers*/ 195aa64c5fbSAnthony Zhou #define MC_SMMU_PPCS_ASID_0 0x270U 19686d0a52bSSamuel Payne #define PPCS_SMMU_ENABLE (0x1U << 31) 19786d0a52bSSamuel Payne 19806b19d58SVarun Wadekar /******************************************************************************* 1997db077f2SVarun Wadekar * Tegra CLDVFS constants 2007db077f2SVarun Wadekar ******************************************************************************/ 2017db077f2SVarun Wadekar #define TEGRA_CL_DVFS_BASE U(0x70110000) 2027db077f2SVarun Wadekar #define DVFS_DFLL_CTRL U(0x00) 2037db077f2SVarun Wadekar #define ENABLE_OPEN_LOOP U(1) 2047db077f2SVarun Wadekar #define ENABLE_CLOSED_LOOP U(2) 2057db077f2SVarun Wadekar #define DVFS_DFLL_OUTPUT_CFG U(0x20) 2067db077f2SVarun Wadekar #define DFLL_OUTPUT_CFG_I2C_EN_BIT (U(1) << 30) 2077db077f2SVarun Wadekar #define DFLL_OUTPUT_CFG_CLK_EN_BIT (U(1) << 6) 2087db077f2SVarun Wadekar 2097db077f2SVarun Wadekar /******************************************************************************* 210ce3c97c9SMarvin Hsu * Tegra SE constants 211ce3c97c9SMarvin Hsu ******************************************************************************/ 212ce3c97c9SMarvin Hsu #define TEGRA_SE1_BASE U(0x70012000) 213ce3c97c9SMarvin Hsu #define TEGRA_SE2_BASE U(0x70412000) 214ce3c97c9SMarvin Hsu #define TEGRA_PKA1_BASE U(0x70420000) 215ce3c97c9SMarvin Hsu #define TEGRA_SE2_RANGE_SIZE U(0x2000) 216ce3c97c9SMarvin Hsu #define SE_TZRAM_SECURITY U(0x4) 217ce3c97c9SMarvin Hsu 218ce3c97c9SMarvin Hsu /******************************************************************************* 21906b19d58SVarun Wadekar * Tegra TZRAM constants 22006b19d58SVarun Wadekar ******************************************************************************/ 22170cb692eSVarun Wadekar #define TEGRA_TZRAM_BASE U(0x7C010000) 22270cb692eSVarun Wadekar #define TEGRA_TZRAM_SIZE U(0x10000) 22306b19d58SVarun Wadekar 2245ed1755aSMarvin Hsu /******************************************************************************* 2255ed1755aSMarvin Hsu * Tegra TZRAM carveout constants 2265ed1755aSMarvin Hsu ******************************************************************************/ 2275ed1755aSMarvin Hsu #define TEGRA_TZRAM_CARVEOUT_BASE U(0x7C04C000) 2285ed1755aSMarvin Hsu #define TEGRA_TZRAM_CARVEOUT_SIZE U(0x4000) 2295ed1755aSMarvin Hsu 230c3cf06f1SAntonio Nino Diaz #endif /* TEGRA_DEF_H */ 231