1*08438e24SVarun Wadekar /* 2*08438e24SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*08438e24SVarun Wadekar * 4*08438e24SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5*08438e24SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6*08438e24SVarun Wadekar * 7*08438e24SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8*08438e24SVarun Wadekar * list of conditions and the following disclaimer. 9*08438e24SVarun Wadekar * 10*08438e24SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11*08438e24SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12*08438e24SVarun Wadekar * and/or other materials provided with the distribution. 13*08438e24SVarun Wadekar * 14*08438e24SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15*08438e24SVarun Wadekar * to endorse or promote products derived from this software without specific 16*08438e24SVarun Wadekar * prior written permission. 17*08438e24SVarun Wadekar * 18*08438e24SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*08438e24SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*08438e24SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*08438e24SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*08438e24SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*08438e24SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*08438e24SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*08438e24SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*08438e24SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*08438e24SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*08438e24SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29*08438e24SVarun Wadekar */ 30*08438e24SVarun Wadekar 31*08438e24SVarun Wadekar #ifndef __TEGRA_DEF_H__ 32*08438e24SVarun Wadekar #define __TEGRA_DEF_H__ 33*08438e24SVarun Wadekar 34*08438e24SVarun Wadekar #include <platform_def.h> 35*08438e24SVarun Wadekar 36*08438e24SVarun Wadekar /******************************************************************************* 37*08438e24SVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 38*08438e24SVarun Wadekar ******************************************************************************/ 39*08438e24SVarun Wadekar #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 40*08438e24SVarun Wadekar #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 41*08438e24SVarun Wadekar #define ACTLR_EL3_L2CTLR_BIT (1 << 4) 42*08438e24SVarun Wadekar #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 43*08438e24SVarun Wadekar #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 44*08438e24SVarun Wadekar #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 45*08438e24SVarun Wadekar ACTLR_EL3_L2ECTLR_BIT | \ 46*08438e24SVarun Wadekar ACTLR_EL3_L2CTLR_BIT | \ 47*08438e24SVarun Wadekar ACTLR_EL3_CPUECTLR_BIT | \ 48*08438e24SVarun Wadekar ACTLR_EL3_CPUACTLR_BIT) 49*08438e24SVarun Wadekar 50*08438e24SVarun Wadekar /******************************************************************************* 51*08438e24SVarun Wadekar * GIC memory map 52*08438e24SVarun Wadekar ******************************************************************************/ 53*08438e24SVarun Wadekar #define TEGRA_GICD_BASE 0x50041000 54*08438e24SVarun Wadekar #define TEGRA_GICC_BASE 0x50042000 55*08438e24SVarun Wadekar 56*08438e24SVarun Wadekar /******************************************************************************* 57*08438e24SVarun Wadekar * Tegra micro-seconds timer constants 58*08438e24SVarun Wadekar ******************************************************************************/ 59*08438e24SVarun Wadekar #define TEGRA_TMRUS_BASE 0x60005010 60*08438e24SVarun Wadekar 61*08438e24SVarun Wadekar /******************************************************************************* 62*08438e24SVarun Wadekar * Tegra Clock and Reset Controller constants 63*08438e24SVarun Wadekar ******************************************************************************/ 64*08438e24SVarun Wadekar #define TEGRA_CAR_RESET_BASE 0x60006000 65*08438e24SVarun Wadekar 66*08438e24SVarun Wadekar /******************************************************************************* 67*08438e24SVarun Wadekar * Tegra Flow Controller constants 68*08438e24SVarun Wadekar ******************************************************************************/ 69*08438e24SVarun Wadekar #define TEGRA_FLOWCTRL_BASE 0x60007000 70*08438e24SVarun Wadekar 71*08438e24SVarun Wadekar /******************************************************************************* 72*08438e24SVarun Wadekar * Tegra Secure Boot Controller constants 73*08438e24SVarun Wadekar ******************************************************************************/ 74*08438e24SVarun Wadekar #define TEGRA_SB_BASE 0x6000C200 75*08438e24SVarun Wadekar 76*08438e24SVarun Wadekar /******************************************************************************* 77*08438e24SVarun Wadekar * Tegra Exception Vectors constants 78*08438e24SVarun Wadekar ******************************************************************************/ 79*08438e24SVarun Wadekar #define TEGRA_EVP_BASE 0x6000F000 80*08438e24SVarun Wadekar 81*08438e24SVarun Wadekar /******************************************************************************* 82*08438e24SVarun Wadekar * Tegra Power Mgmt Controller constants 83*08438e24SVarun Wadekar ******************************************************************************/ 84*08438e24SVarun Wadekar #define TEGRA_PMC_BASE 0x7000E400 85*08438e24SVarun Wadekar 86*08438e24SVarun Wadekar /******************************************************************************* 87*08438e24SVarun Wadekar * Tegra Memory Controller constants 88*08438e24SVarun Wadekar ******************************************************************************/ 89*08438e24SVarun Wadekar #define TEGRA_MC_BASE 0x70019000 90*08438e24SVarun Wadekar 91*08438e24SVarun Wadekar #endif /* __TEGRA_DEF_H__ */ 92